Semiconductor device and manufacturing method for the same

ABSTRACT

An object is to provide a method for manufacturing a highly reliable semiconductor device including thin film transistors which have stable electric characteristics and are formed using an oxide semiconductor. A method for manufacturing a semiconductor device includes the steps of: forming an oxide semiconductor film over a gate electrode with a gate insulating film interposed between the oxide semiconductor film and the gate electrode, over an insulating surface; forming a first conductive film including at least one of titanium, molybdenum, and tungsten, over the oxide semiconductor film; forming a second conductive film including a metal having lower electronegativity than hydrogen, over the first conductive film; forming a source electrode and a drain electrode by etching of the first conductive film and the second conductive film; and forming an insulating film in contact with the oxide semiconductor film, over the oxide semiconductor film, the source electrode, and the drain electrode.

TECHNICAL FIELD

The present invention relates to a semiconductor device including anoxide semiconductor and a manufacturing method thereof.

BACKGROUND ART

A thin film transistor formed using a semiconductor film formed over aninsulating surface is a semiconductor element which is essential for asemiconductor device. Since a restriction of the allowable temperaturelimit of a substrate is imposed on manufacture of a thin filmtransistor, thin film transistors having active layers includingamorphous silicon which can be deposited at relatively low temperature,polysilicon which is obtained in such a manner that crystallization isperformed using laser light or a catalyst element, or the like becomethe mainstream of transistors used for semiconductor display devices.

In recent years, a metal oxide showing semiconductor characteristics hasattracted attention, which is called an oxide semiconductor as a novelsemiconductor material having high mobility obtained by polysilicon andhaving uniform element characteristics obtained by amorphous silicon.The metal oxide is used for various applications. For example, indiumoxide is a well-known metal oxide and used as a material of atransparent electrode included in a liquid crystal display device or thelike. Examples of such metal oxides having semiconductor characteristicsinclude tungsten oxide, tin oxide, indium oxide, and zinc oxide. Thinfilm transistors in each of which a channel formation region is formedusing such a metal oxide having semiconductor characteristics have beenknown (Patent Documents 1 and 2).

REFERENCE

-   [Patent Document 1] Japanese Published Patent Application No.    2007-123861-   [Patent Document 2] Japanese Published Patent Application No.    2007-096055

DISCLOSURE OF INVENTION

Transistors used for semiconductor devices preferably have smallvariation in threshold voltage, which is caused by degradation overtime, and good properties in on-state current or the like. Whentransistors having small variation in threshold voltage, which is causedby degradation over time are used, reliability of semiconductor devicescan be increased. In addition, when transistors having goodcharacteristics such as on-state current are used, semiconductor devicescan be driven at a higher frequency.

It is an object of the present invention to provide a method formanufacturing a highly reliable semiconductor device. Alternatively, itis an object of the present invention to provide a method formanufacturing a semiconductor device which can operate at high speed.Alternatively, an object of the present invention is to provide a highlyreliable semiconductor device. Alternatively, an object of the presentinvention is to provide a semiconductor device which can operate at highspeed.

The present inventors have paid their attention to the fact thatimpurities such as hydrogen or water existing in an oxide semiconductorfilm cause degradation over time, such as shifts in threshold voltage,to transistors. Then, they have thought that a conductive film formedusing a low electronegativity metal, specifically, a metal of lowerelectronegativity than hydrogen is used as a conductive film for asource electrode or a drain electrode and is formed over or below anoxide semiconductor film, so that impurities such as hydrogen or waterexisting in the oxide semiconductor film are extracted by the conductivefilm and purity of the oxide semiconductor film is increased;consequently, degradation of transistors over time due to the impuritiessuch as hydrogen or water can be suppressed. The conductive film isprocessed into a desired shape by etching or the like, so that a sourceelectrode and a drain electrode can be formed.

Specifically, according to one embodiment of the present invention, inmanufacture of a semiconductor device having a transistor in which anoxide semiconductor film is used for an active layer, a first conductivefilm formed using a metal material having low contact resistance to theoxide semiconductor film, such as titanium, tungsten, or molybdenum, isformed so as to be in contact with the oxide semiconductor film. Inaddition, a second conductive film formed using a low electronegativitymetal, a low electronegativity metal compound, or a lowelectronegativity alloy is formed so as to overlap with the oxidesemiconductor film with the first conductive film between the secondconductive film and the oxide semiconductor film. Then, the firstconductive film and the second conductive film are processed intodesired shapes by etching or the like, whereby a source electrode and adrain electrode are formed.

Alternatively, the first conductive film is formed so as to be incontact with the oxide semiconductor film, and the second conductivefilm is formed so as to overlap with the oxide semiconductor film withthe first conductive film between the second conductive film and theoxide semiconductor film, and then the second conductive film is removedby etching. In this case, after the second conductive film is removed, athird conductive film formed using a low electronegativity metal, a lowelectronegativity metal compound, or a low electronegativity alloy isadditionally formed so as to overlap with the oxide semiconductor filmwith the first conductive film between the third conductive film and theoxide semiconductor film. Then, the first conductive film and the thirdconductive film are processed into desired shapes by etching or thelike, whereby the source electrode and the drain electrode are formed.

Further alternatively, the first conductive film is formed so as to bein contact with the oxide semiconductor film, and the second conductivefilm is formed so as to overlap with the oxide semiconductor film withthe first conductive film between the second conductive film and theoxide semiconductor film, and then the second conductive film is removedby etching. Next, after the second conductive film is removed, the thirdconductive film formed using a low electronegativity metal, a lowelectronegativity metal compound, or a low electronegativity alloy isformed so as to overlap with the oxide semiconductor film with the firstconductive film between the third conductive film and the oxidesemiconductor film. Further, over the third conductive film, a fourthconductive film formed using a metal material having low contactresistance to the oxide semiconductor film, such as titanium, tungsten,or molybdenum, is formed so as to overlap with the oxide semiconductorfilm. Note that in the case, a fifth conductive film formed using ametal material having low contact resistance to the oxide semiconductorfilm, such as titanium, tungsten, or molybdenum may be formed betweenthe first conductive film and the third conductive film. Then, the firstconductive film, the third conductive film, and the fourth conductivefilm, or the first conductive film, the third conductive film, thefourth conductive film, and the fifth conductive film are formed byprocessed into desired shapes by etching or the like, whereby the sourceelectrode and the drain electrode are formed.

According to one embodiment of the present invention, the metal materialhaving low contact resistance to the oxide semiconductor film is usedfor the first conductive film forming the source electrode and the drainelectrode, and the first conductive film is in contact with the oxidesemiconductor film, so that contact resistance between the source ordrain electrode and the oxide semiconductor film is reduced.Accordingly, on-state current and field-effect mobility of a TFT can beincreased. In addition, the second conductive film and the thirdconductive film are formed using a low electronegativity metal, a lowelectronegativity metal compound, or a low electronegativity alloy, sothat impurities such as moisture or hydrogen existing in the oxidesemiconductor film, a gate insulating film, or at an interface betweenthe oxide semiconductor film and another insulating film and thevicinity thereof are occluded or adsorbed by the second conductive filmor the third conductive film. Therefore, by elimination of impuritiessuch as moisture or hydrogen, an oxide semiconductor which is anintrinsic (i-type) semiconductor or a substantially i-type semiconductorcan be obtained, and deterioration of characteristics of the transistordue to the impurities, such as shifts in threshold voltage, can beprevented from being promoted and off-state current can be reduced.

As the low electronegativity metal, aluminum, magnesium, and the likecan be given. A mixture, a metal compound, or an alloy each includingone or more of the above metals can be used for the second conductivefilm and the third conductive film. Alternatively, a heat-resistantconductive material such as an element selected from titanium, tantalum,tungsten, molybdenum, chromium, neodymium, or scandium; an alloycontaining one or more of the above elements as a component; nitridecontaining any of the above elements as a component is combined withaluminum to be used as the second conductive film and the thirdconductive film.

Note that among the above metal having low contact resistance to theoxide semiconductor film, electronegativity of titanium is lower thanthat of hydrogen; therefore, impurities such as moisture or hydrogen areeasily extracted from the oxide semiconductor film. Therefore, titaniumis used for the first conductive film, the fourth conductive film, andthe fifth conductive film, so that impurities in the oxide semiconductorfilm can be reduced and the source electrode and the drain electrodewhich have low contact resistance to the oxide semiconductor film can beformed.

In addition to the above structure, while the second conductive film,the third conductive film, or the fourth conductive film is exposed,heat treatment is performed under a reduced atmosphere or an inert gasatmosphere, so that moisture, oxygen, or the like which is adsorbed on asurface of or inside the second conductive film, the third conductivefilm, or the fourth conductive film may be removed. The temperaturerange of the heat treatment is 200° C. to 450° C. The heat treatment isperformed, so that impurities such as moisture or hydrogen existing inthe oxide semiconductor film, the gate insulating film, or at theinterface between the oxide semiconductor film and another insulatingfilm and the vicinity thereof can be easily occluded or adsorbed by thesecond conductive film, the third conductive film, or the fourthconductive film.

After the source electrode and the drain electrode are formed, asingle-layer insulating film or a plurality of insulating films stackedmay be formed so as to cover the source electrode, the drain electrode,and the oxide semiconductor film. A material having a high barrierproperty is preferably used for the insulating film. For example, as theinsulating film having a high barrier property, a silicon nitride film,a silicon nitride oxide film, an aluminum nitride film, an aluminumnitride oxide film, or the like can be used. When a plurality ofinsulating films stacked is used, an insulating film having lowerproportion of nitrogen than the insulating film having a barrierproperty, such as a silicon oxide film or a silicon oxynitride film, isformed on the side close to the oxide semiconductor film. Then, theinsulating film having a barrier property is formed so as to overlapwith the source electrode, the drain electrode, and the oxidesemiconductor film with the insulating film having lower proportion ofnitrogen between the insulating film having a barrier property and thesource electrode, the drain electrode, and the oxide semiconductor film.When the insulating film having a barrier property is used, moisture oroxygen can be prevented from being adsorbed on the surface of or insidethe conductive film. In addition, the impurities such as moisture orhydrogen can be prevented from entering the oxide semiconductor film,the gate insulating film, or at the interface between the oxidesemiconductor film and another insulating film and the vicinity thereof.

In addition, between a gate electrode and the oxide semiconductor film,a gate insulating film may be formed to have a structure in which aninsulating film formed using a material having a high barrier property,and an insulating film having lower proportion of nitrogen, such as asilicon oxide film or a silicon oxynitride film, are stacked. Theinsulating film such as a silicon oxide film or a silicon oxynitridefilm is formed between the insulating film having a barrier property andthe oxide semiconductor film. The insulating film having a barrierproperty is used, so that impurities in an atmosphere, such as moistureor hydrogen, or impurities included in a substrate, such as an alkalimetal or a heavy metal, can be prevented from entering the oxidesemiconductor film, the gate insulating film, or at the interfacebetween the oxide semiconductor film and another insulating film and thevicinity thereof.

To reduce impurities such as moisture or hydrogen in the oxidesemiconductor film, after the oxide semiconductor film is formed, heattreatment is performed in an inert gas atmosphere such as a nitrogenatmosphere or a rare gas (argon, helium, or the like) atmosphere whilethe oxide semiconductor film is exposed. The temperature range of theheat treatment is preferably higher than or equal to 500° C. and lowerthan or equal to 750° C. (or temperature of lower than or equal to astrain point of a glass substrate). Note that this heat treatment isperformed at a temperature not exceeding the allowable temperature limitof the substrate to be used.

As the oxide semiconductor, a four-component metal oxide such as anIn—Sn—Ga—Zn—O-based oxide semiconductor, a three-component metal oxidesuch as an In—Ga—Zn—O-based oxide semiconductor, an In—Sn—Zn—O-basedoxide semiconductor, an In—Al—Zn—O-based oxide semiconductor, aSn—Ga—Zn—O-based oxide semiconductor, an Al—Ga—Zn—O-based oxidesemiconductor, and a Sn—Al—Zn—O-based oxide semiconductor, or atwo-component metal oxide such as an In—Zn—O-based oxide semiconductor,a Sn—Zn—O-based oxide semiconductor, an Al—Zn—O-based oxidesemiconductor, a Zn—Mg—O-based oxide semiconductor, a Sn—Mg—O-basedoxide semiconductor, an In—Mg—O-based oxide semiconductor, anIn—Ga—O-based oxide semiconductor, an In—O-based oxide semiconductor, aSn—O-based oxide semiconductor, and a Zn—O-based oxide semiconductor canbe used. Note that in this specification, for example, anIn—Sn—Ga—Zn—O-based oxide semiconductor means a metal oxide includingindium (In), tin (Sn), gallium (Ga), and zinc (Zn). There is noparticular limitation on the composition ratio. The above oxidesemiconductor may include silicon.

Alternatively, oxide semiconductors can be represented by the chemicalformula, InMO₃(ZnO)_(m) (m>0). Here, M represents one or more metalelements selected from Ga, Al, Mn, or Co.

Note that impurities such as moisture in the oxide semiconductor filmare eliminated by the heat treatment, so that carrier concentration isincreased and resistance is reduced. Then, when an insulating film suchas a silicon oxide film or a silicon oxynitride film is formed so as tobe in contact with the oxide semiconductor film with reduced resistance,oxygen is supplied to at least a region of the oxide semiconductor filmwith reduced resistance which is in contact with the insulating film, sothat carrier concentration is reduced (preferably, less than 1×10¹⁸/cm³,more preferably less than or equal to 1×10¹⁴/cm³) and resistance isincreased. In this manner, carrier concentration and resistance of theoxide semiconductor film can be controlled by the formation of theinsulating film such as a silicon oxide film or a silicon oxynitridefilm in a process of a semiconductor device; therefore, a semiconductordevice having a thin film transistor which has good electriccharacteristics and good reliability can be manufactured and provided.

The transistor may be a bottom gate transistor, a top gate transistor,or a bottom contact transistor. A bottom gate transistor has a gateelectrode over an insulating surface; a gate insulating film over thegate electrode; an oxide semiconductor film which is over the gateinsulating film and which overlaps with the gate electrode; a sourceelectrode and a drain electrode which are over the oxide semiconductorfilm; and an insulating film over the source electrode, the drainelectrode, and the oxide semiconductor film. A top gate transistor hasan oxide semiconductor film over an insulating surface; a gateinsulating film over the oxide semiconductor film; a gate electrodewhich overlaps with the oxide semiconductor film over the gateinsulating film and functions as a conductive film; a source electrode;a drain electrode; and an insulating film over the source electrode, thedrain electrode, and the oxide semiconductor film. A bottom contacttransistor has a gate electrode over an insulating surface; a gateinsulating film over the gate electrode; a source electrode and a drainelectrode which are over the gate insulating film; an oxidesemiconductor film which is over the source electrode and the drainelectrode and which overlaps with the gate electrode over the gateinsulating film; and an insulating film over the source electrode, thedrain electrode, and the oxide semiconductor film.

For the heat treatment, heat treatment in a furnace or a rapid thermalannealing method (RTA method) is used. As the RTA method, a method usinga lamp light source or a method in which heat treatment is performed fora short time while a substrate is moved in a heated gas can be employed.With the use of the RTA method, it is also possible to make the timenecessary for heat treatment shorter than 0.1 hours. Note that in thecase where a glass substrate is used as a substrate, heat treatment isperformed at higher than or equal to 300° C. and less than or equal tothe strain point of the glass substrate.

A method for manufacturing a semiconductor device with high reliabilitycan be provided. In addition, a method for manufacturing a semiconductordevice which can operate at high speed can be provided. Further, ahighly reliable semiconductor device can be provided. In addition, asemiconductor device which can operate at high speed can be provided.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1A to 1E are cross-sectional views illustrating a method formanufacturing a semiconductor device.

FIG. 2 is a top view of a thin film transistor.

FIGS. 3A and 3B are cross-sectional views of a thin film transistor andFIG. 3C is a top view of a thin film transistor.

FIGS. 4A to 4D are cross-sectional views illustrating a method formanufacturing a semiconductor device.

FIGS. 5A to 5D are cross-sectional views illustrating a method formanufacturing a semiconductor device.

FIGS. 6A to 6D are cross-sectional views illustrating a method formanufacturing a semiconductor device.

FIGS. 7A to 7E are cross-sectional views of a thin film transistor.

FIG. 8 is a top view of a thin film transistor.

FIGS. 9A and 9B are cross-sectional views of a thin film transistor andFIG. 9C is a top view of a thin film transistor.

FIGS. 10A to 10E are cross-sectional views of a thin film transistor.

FIG. 11 is a top view of a thin film transistor.

FIGS. 12A to 12C are cross-sectional views illustrating a method formanufacturing a semiconductor device.

FIGS. 13A and 13B are cross-sectional views illustrating a method formanufacturing a semiconductor device.

FIGS. 14A and 14B are cross-sectional views illustrating a method formanufacturing a semiconductor device.

FIG. 15 is a top view illustrating a method for manufacturing asemiconductor device.

FIG. 16 is a top view illustrating a method for manufacturing asemiconductor device.

FIG. 17 is a top view illustrating a method for manufacturing asemiconductor device.

FIG. 18A is a top view of electronic paper and FIG. 18B is across-sectional view of electronic paper.

FIGS. 19A and 19B are bloc diagrams of semiconductor display devices.

FIG. 20A is a diagram of a structure of a signal line driver circuit andFIG. 20B is a timing chart.

FIGS. 21A and 21B are circuit diagrams illustrating a structure of ashift register.

FIG. 22A is a circuit diagram and FIG. 22B is a timing chartillustrating operations of a shift register.

FIG. 23 is a cross-sectional view of a liquid crystal display device.

FIG. 24 is a view illustrating a structure of a liquid crystal displaydevice module.

FIGS. 25A to 25C are cross-sectional views of light-emitting devices.

FIGS. 26A to 26E are diagrams each illustrating an electronic deviceincluding a semiconductor device.

FIG. 27 is a cross-sectional view of an inverted staggered thin filmtransistor formed using an oxide semiconductor.

FIGS. 28A and 28B are energy band diagrams (schematic diagrams) of across-section taken along line A-A′ in FIG. 27.

FIG. 29A is a view illustrating a state where a positive potential (+VG)is applied to a gate (GI), and FIG. 29B is a view illustrating a statewhere a negative potential (−VG) is applied to the gate (GI).

FIG. 30 is a view illustrating a relation among a vacuum level, a workfunction (φ_(M)) of a metal and an electron affinity (χ) of an oxidesemiconductor.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described indetail with reference to the accompanying drawings. However, the presentinvention is not limited to the following description and it is easilyunderstood by those skilled in the art that the mode and details can bechanged in various ways without departing from the spirit and scope ofthe present invention. Accordingly, the present invention should not beconstrued as being limited to the description of the embodiments below.

The present invention can be applied to manufacture of any kind ofsemiconductor devices including microprocessors, integrated circuitssuch as image processing circuits, RF tags, and semiconductor displaydevices. A semiconductor device means any device which can function byutilizing semiconductor characteristics, and a semiconductor displaydevice, a semiconductor circuit, and an electronic device are allincluded in the category of the semiconductor device. The semiconductordisplay devices include the following in its category: liquid crystaldisplay devices, light-emitting devices in which a light-emittingelement typified by an organic light-emitting element (OLED) is providedfor each pixel, electronic paper, digital micromirror devices (DMDs),plasma display panels (PDPs), field emission displays (FEDs), and othersemiconductor display devices in which a circuit element using asemiconductor film is included in a driver circuit.

Embodiment 1

A method for manufacturing a semiconductor device will be described withreference to FIGS. 1A to 1E, FIG. 2, and FIGS. 3A to 3C using a bottomgate thin film transistor having a channel etched structure as anexample.

As illustrated in FIG. 1A, a gate electrode 101 is formed over asubstrate 100.

An insulating film to serve as a base film may be formed between thesubstrate 100 and the gate electrode 101. As the base film, for example,a single layer of a silicon oxide film, a silicon oxynitride film, asilicon nitride film, a silicon nitride oxide film, an aluminum nitridefilm, or an aluminum nitride oxide film or a stacked layer of aplurality of these films can be used. In particular, an insulating filmhaving a high barrier property, for example, a silicon nitride film, asilicon nitride oxide film, an aluminum nitride film, or an aluminumnitride oxide film is used for the base film, so that impurities in anatmosphere, such as moisture or hydrogen, or impurities included in thesubstrate 100, such as an alkali metal or a heavy metal, can beprevented from entering the oxide semiconductor film, the gateinsulating film or at the interface between the oxide semiconductor filmand another insulating film and the vicinity thereof.

In this specification, oxynitride refers to a substance which includesmore oxygen than nitrogen, and nitride oxide refers to a substance whichincludes more nitrogen than oxygen.

The gate electrode 101 can be formed with a single layer or a stackedlayer using one or more of conductive films using a metal material suchas molybdenum, titanium, chromium, tantalum, tungsten, neodymium, orscandium; an alloy material which includes any of these metal materialsas a main component; or a nitride of any of these metals. Note thataluminum or copper can be used as the metal material as long as aluminumor copper can withstand temperature of heat treatment to be performed ina later process. Aluminum or copper is preferably combined with arefractory metal material so as to prevent a heat resistance problem anda corrosive problem. As the refractory metal material, molybdenum,titanium, chromium, tantalum, tungsten, neodymium, scandium, or the likecan be used.

For example, as a two-layer structure of the gate electrode 101, thefollowing structures are preferable: a two-layer structure in which amolybdenum film is stacked over an aluminum film, a two-layer structurein which a molybdenum film is stacked over a copper film, a two-layerstructure in which a titanium nitride film or a tantalum nitride film isstacked over a copper film, and a two-layer structure in which atitanium nitride film and a molybdenum film are stacked. As athree-layer structure of the gate electrode 101, the following structureis preferable: a stacked structure containing an aluminum film, an alloyfilm of aluminum and silicon, an alloy film of aluminum and titanium, oran alloy film of aluminum and neodymium in a middle layer and any of atungsten film, a tungsten nitride film, a titanium nitride film, and atitanium film in a top layer and a bottom layer.

Further, a light-transmitting oxide conductive film of indium oxide, analloy of indium oxide and tin oxide, an alloy of indium oxide and zincoxide, zinc oxide, aluminum zinc oxide, aluminum zinc oxynitride,gallium zinc oxide, or the like is used as the gate electrode 101, sothat the aperture ratio of a pixel portion can be increased.

The thickness of the gate electrode 101 is 10 nm to 400 nm, preferably100 nm to 200 nm. In this embodiment, after the conductive film for thegate electrode is formed to have a thickness of 150 nm formed with asputtering method using a tungsten target, the conductive film isprocessed (patterned) into a desired shape by etching, whereby the gateelectrode 101 is formed.

Next, a gate insulating film 102 is formed over the gate electrode 101.The gate insulating film 102 can be formed to have a single layer of asilicon oxide film, a silicon nitride film, a silicon oxynitride film, asilicon nitride oxide film, an aluminum oxide film, or a tantalum oxidefilm, or a stacked layer thereof with a plasma enhanced CVD method, asputtering method, or the like. It is preferable that the gateinsulating film 102 include impurities such as moisture or hydrogen aslittle as possible. The gate insulating film 102 may have a structure inwhich an insulating film formed using a material having a high barrierproperty and an insulating film having lower proportion of nitrogen suchas a silicon oxide film or a silicon oxynitride film are stacked. Inthis case, the insulating film such as a silicon oxide film or a siliconoxynitride film is formed between the insulating film having a barrierproperty and the oxide semiconductor film. As the insulating film havinga high barrier property, a silicon nitride film, a silicon nitride oxidefilm, an aluminum nitride film, an aluminum nitride oxide film, or thelike can be given, for example. The insulating film having a barrierproperty is used, so that impurities in an atmosphere, such as moistureor hydrogen, or impurities included in the substrate, such as an alkalimetal or a heavy metal, can be prevented from entering the oxidesemiconductor film, the gate insulating film 102, or at the interfacebetween the oxide semiconductor film and another insulating film and thevicinity thereof. In addition, the insulating film having lowerproportion of nitrogen such as a silicon oxide film or a siliconoxynitride film is formed so as to be in contact with the oxidesemiconductor film, so that the insulating film formed using a materialhaving a high barrier property can be prevented from being in contactwith the oxide semiconductor film directly.

In this embodiment, the gate insulating film 102 having a structure inwhich a silicon oxide film having a thickness of 100 nm formed with asputtering method is stacked over a silicon nitride film having athickness of 50 nm formed with a sputtering method is formed.

Next, an oxide semiconductor film is formed over the gate insulatingfilm 102. The oxide semiconductor film is formed with a sputteringmethod using an oxide semiconductor as a target. Moreover, the oxidesemiconductor film can be formed with a sputtering method in a rare gas(for example, argon) atmosphere, an oxygen atmosphere, or an atmosphereincluding a rare gas (for example, argon) and oxygen.

Note that before the oxide semiconductor film is formed with asputtering method, dust attached to a surface of the gate insulatingfilm 102 is preferably removed by reverse sputtering in which an argongas is introduced and plasma is generated. The reverse sputtering refersto a method in which, without application of voltage to a target side,an RF power supply is used for application of voltage to a substrateside in an argon atmosphere and plasma is generated in the vicinity ofthe substrate to modify a surface. Note that instead of an argonatmosphere, a nitrogen atmosphere, a helium atmosphere, or the like maybe used. Alternatively, an argon atmosphere to which oxygen, nitrousoxide, or the like is added may be used. Alternatively, an argonatmosphere to which chlorine, carbon tetrafluoride, or the like is addedmay be used.

For the oxide semiconductor film, the above-described oxidesemiconductor can be used.

The thickness of the oxide semiconductor film is set to 10 nm to 300 nm,preferably, 20 nm to 100 nm. In this embodiment, as the oxidesemiconductor film, an In—Ga—Zn—O-based oxide semiconductor film with athickness of 30 nm, which is obtained with a sputtering method using anoxide semiconductor target including indium (In), gallium (Ga), and zinc(Zn) (In₂O₃:Ga₂O₃:ZnO=1:1:1 or 1:1:2 in a molar ratio), is used. In thisembodiment, a DC sputtering method is employed, a flow rate of argon is30 sccm, a flow rate of oxygen is 15 sccm, and a substrate temperatureis a room temperature.

The gate insulating film 102 and the oxide semiconductor film may beformed successively without exposure to air. Successive film formationwithout exposure to air makes it possible to obtain each interfacebetween stacked layers, which is not contaminated by atmosphericcomponents or impurity elements floating in air, such as water,hydrocarbon, or the like. Therefore, variation in characteristics of thethin film transistor can be reduced.

Next, as illustrated in FIG. 1A, the oxide semiconductor film isprocessed (patterned) into a desired shape by etching or the like,whereby an island-shaped oxide semiconductor film 103 is formed over thegate insulating film 102 in a position where the island-shaped oxidesemiconductor film 103 overlaps with the gate electrode 101.

Next, in an inert gas atmosphere (nitrogen, helium, neon, argon, or thelike), heat treatment may be performed on the oxide semiconductor film103. When the heat treatment is performed on the oxide semiconductorfilm 103, an oxide semiconductor film 104 in which moisture or hydrogenis eliminated is formed. Specifically, in a reduced atmosphere, an inertgas atmosphere such as a nitrogen atmosphere or a rare gas atmosphere,an oxygen gas atmosphere, or an ultra dry air atmosphere (in air whosemoisture content is less than or equal to 20 ppm (dew point conversion,−55° C.), preferably, less than or equal to 1 ppm, more preferably, lessthan or equal to 10 ppb in the case where measurement is performed usinga dew-point meter of a cavity ring-down laser spectroscopy (CRDS)system), rapid thermal annealing (RTA) treatment can be performed at atemperature of higher than or equal to 500° C. and lower than or equalto 750° C. (or lower than or equal to a strain point of a glasssubstrate) for approximately greater than or equal to one minute andless than or equal to ten minutes, preferably, at 600° C. forapproximately greater than or equal to three minutes and less than orequal to six minutes. With an RTA method, dehydration or dehydrogenationcan be performed in a short time; therefore, treatment can be performedeven at a temperature higher than the strain point of the glasssubstrate. Note that the heat treatment is not necessarily performedafter the island-shaped oxide semiconductor film 103 is formed, and theheat treatment may be performed on the oxide semiconductor film beforethe island-shaped oxide semiconductor film 103 is formed. The heattreatment may be performed more than once after the oxide semiconductorfilm 104 is formed. Impurities such as moisture or hydrogen areeliminated by the heat treatment, so that the island-shaped oxidesemiconductor film 104 becomes an intrinsic (i-type) semiconductor or asubstantially i-type semiconductor; therefore, deterioration ofcharacteristics of the transistor due to the impurities, such as shiftsin threshold voltage, can be prevented from being promoted and off-statecurrent can be reduced.

In this embodiment, heat treatment is performed in a nitrogen atmosphereat 600° C. for six minutes in a state where the substrate temperaturereaches the set temperature. Further, a heating method using an electricfurnace, a rapid heating method such as a gas rapid thermal annealing(GRTA) method using a heated gas or a lamp rapid thermal annealing(LRTA) method using lamp light, or the like can be used for the heattreatment. For example, in the case of performing heat treatment usingan electric furnace, the temperature rise characteristics are preferablyset at higher than or equal to 0.1° C./min and lower than or equal to20° C./min and the temperature drop characteristics are preferably setat higher than or equal to 0.1° C./min and lower than or equal to 15°C./min.

Note that it is preferable that in the heat treatment, moisture,hydrogen, or the like be not contained in nitrogen or a rare gas such ashelium, neon, or argon. Alternatively, it is preferable that the purityof nitrogen or the rare gas such as helium, neon, or argon which isintroduced into a heat treatment apparatus be set to be higher than orequal to 6N (99.9999%), preferably higher than or equal to 7N(99.99999%) (that is, the impurity concentration is lower than or equalto 1 ppm, preferably lower than or equal to 0.1 ppm).

Next, as illustrated in FIG. 1C, a conductive film used for a sourceelectrode and a drain electrode is formed over the island-shaped oxidesemiconductor film 104. In this embodiment, a conductive film 105 bformed using a low electronegativity metal, a low electronegativitymetal compound, or a low electronegativity alloy is formed over aconductive film 105 a formed using a metal material which has lowcontact resistance to the oxide semiconductor film 104, such astitanium, tungsten, or molybdenum.

As the low electronegativity metal, aluminum or magnesium can also beused. A mixture, a metal compound, or an alloy each including one ormore of the above metals can be used for the conductive film 105 b. Whena low heat-resistance material such as aluminum is used, aluminum iscombined with a heat-resistant conductive material such as an elementselected from titanium, tantalum, tungsten, molybdenum, chromium,neodymium, or scandium; an alloy containing one or more of theseelements as its component; or nitride containing the element as itscomponent, so that heat resistance of the conductive film 105 b may beincreased.

The thickness of the conductive film 105 a is preferably 10 nm to 200nm, more preferably, 50 nm to 150 nm. The thickness of the conductivefilm 105 b is preferably 100 nm to 300 nm, more preferably, 150 nm to250 nm. In this embodiment, a titanium film having a thickness of 100 nmformed with a sputtering method is used as the conductive film 105 a,and an aluminum film having a thickness of 200 nm formed with asputtering method is used as the conductive film 105 b.

In one embodiment of the present invention, the conductive film 105 b isformed using a low electronegativity metal, a low electronegativitymetal compound, or a low electronegativity alloy, so that impuritiessuch as moisture or hydrogen existing in the oxide semiconductor film104, the gate insulating film 102, or at an interface between the oxidesemiconductor film 104 and another insulating film and the vicinitythereof are occluded or adsorbed by the conductive film 105 b.Therefore, by elimination of impurities such as moisture or hydrogen,the oxide semiconductor film 104 which is an intrinsic (i-type)semiconductor or a substantially i-type semiconductor can be obtained,and deterioration of characteristics of the transistor due to theimpurities, such as shifts in threshold voltage, can be prevented frombeing promoted and off-state current can be reduced.

In addition to above structure, the exposed conductive film 105 b issubjected to heat treatment in a reduced atmosphere, or an inert gasatmosphere such as a nitrogen atmosphere or a rare gas (argon, helium,or the like) atmosphere, so that moisture, oxygen, or the like adsorbedon the surface of or inside the conductive film 105 b may be removed.The temperature range of the heat treatment is 200° C. to 450° C. Theheat treatment is performed, so that impurities such as moisture orhydrogen existing in the oxide semiconductor film 104, the gateinsulating film 102 or at the interface between the oxide semiconductorfilm 104 and another insulating film and the vicinity thereof can beeasily occluded or adsorbed by the conductive film 105 b.

Next, as illustrated in FIG. 1D, the conductive film 105 a and theconductive film 105 b are processed (patterned) into desired shapes byetching or the like, whereby a source electrode 106 and a drainelectrode 107 are formed. For example, when a titanium film is used forthe conductive film 105 a and an aluminum film is used for theconductive film 105 b, after wet etching is performed on the conductivefilm 105 b using a solution containing phosphoric acid, wet etching maybe performed on the conductive film 105 a using a solution (ammoniaperoxide mixture) containing ammonia and oxygenated water. Specifically,in this embodiment, an Al-Etchant (an aqueous solution containing nitricacid of 2.0 wt %, acetic acid of 9.8 wt %, and phosphoric acid of 72.3wt %) produced by Wako Pure Chemical Industries, Ltd. is used as thesolution containing phosphoric acid. In addition, as the ammoniaperoxide mixture, specifically, a solution in which oxygenated water of31 wt %, ammonia water of 28 wt %, and water are mixed at a volume ratioof 5:2:2 is used. Alternatively, dry etching may be performed on theconductive film 105 a and the conductive film 105 b using a gascontaining chlorine (Cl₂), boron chloride (BCl₃), or the like.

When the source electrode 106 and the drain electrode 107 are formed bythe patterning, part of an exposed portion of the island-shaped oxidesemiconductor film 104 is etched, so that a groove (a depressed portion)is formed in some cases. In this embodiment, the case in which anisland-shaped oxide semiconductor film 108 having a groove (a depressedportion) is formed by the etching is described. The conductive film 105a serving as part of the source electrode 106 and the drain electrode107 is in contact with the oxide semiconductor film 108. In addition,since the conductive film 105 a is formed using a metal material havinglow contact resistance to the oxide semiconductor film 108 as describedabove, contact resistance between the source electrode 106 or the drainelectrode 107 and the oxide semiconductor film 108 is reduced.Accordingly, on-state current and field-effect mobility of a TFT can beincreased.

Note that as illustrated in FIG. 1E, after the source electrode 106 andthe drain electrode 107 are formed, an insulating film 109 is formed soas to cover the source electrode 106, the drain electrode 107, and theoxide semiconductor film 108. The insulating film 109 preferablyincludes impurities such as moisture or hydrogen as little as possible,and the insulating film 109 may be formed using a single-layerinsulating film or a plurality of insulating films stacked. A materialhaving a high barrier property is preferably used for the insulatingfilm 109. For example, as the insulating film having a high barrierproperty, a silicon nitride film, a silicon nitride oxide film, analuminum nitride film, an aluminum nitride oxide film, or the like canbe used. When a plurality of insulating films stacked is used, aninsulating film having lower proportion of nitrogen than the insulatingfilm having a barrier property, such as a silicon oxide film or asilicon oxynitride film, is formed on the side close to the oxidesemiconductor film 108. Then, the insulating film having a barrierproperty is formed so as to overlap with the source electrode 106, thedrain electrode 107, and the oxide semiconductor film 108 with theinsulating film having lower proportion of nitrogen between theinsulating film having a barrier property and the source electrode 106,the drain electrode 107, and the oxide semiconductor film 108. When theinsulating film having a barrier property is used, moisture or oxygencan be prevented from being adsorbed on the surfaces of or inside thesource electrode 106 and the drain electrode 107. In addition, theimpurities such as moisture or hydrogen can be prevented from enteringthe oxide semiconductor film 108, the gate insulating film 102, or atthe interface between the oxide semiconductor film 108 and anotherinsulating film and the vicinity thereof. In addition, the insulatingfilm having lower proportion of nitrogen such as a silicon oxide film ora silicon oxynitride film is formed so as to be in contact with theoxide semiconductor film 108, so that the insulating film formed using amaterial having a high barrier property can be prevented from being incontact with the oxide semiconductor film directly.

In this embodiment, the insulating film 109 having a structure in whicha silicon nitride film having a thickness of 100 nm formed with asputtering method is stacked over a silicon oxide film having athickness of 200 nm formed with a sputtering method is formed. Thesubstrate temperature in film formation may be higher than or equal toroom temperature and lower than or equal to 300° C. and in thisembodiment, is 100° C.

An exposed region of the oxide semiconductor film 108 provided betweenthe source electrode 106 and the drain electrode 107 and the siliconoxide film which forms the insulating film 109 are provided in contactwith each other, so that oxygen is supplied to the region of the oxidesemiconductor film 108, which is in contact with the insulating film109, and resistance of the region is increased (carrier concentration isdecreased, preferably, less than 1×10¹⁸/cm³), whereby the oxidesemiconductor film 108 having a channel formation region with highresistance can be formed.

Note that after the insulating film 109 is formed, heat treatment may beperformed. The heat treatment is preferably performed at higher than orequal to 200° C. and lower than or equal to 400° C., for example, higherthan or equal to 250° C. and lower than or equal to 350° C. in an airatmosphere, a reduced atmosphere, an inert gas atmosphere such as anitrogen atmosphere or a rare gas atmosphere, an oxygen gas atmosphere,or an ultra dry air atmosphere (in air whose moisture content is lessthan or equal to 20 ppm (dew point conversion, −55° C.), preferably,less than or equal to 1 ppm, more preferably, less than or equal to 10ppb in the case where measurement is performed using a dew-point meterof a cavity ring-down laser spectroscopy (CRDS) system). For example,the heat treatment is performed at 250° C. for one hour in a nitrogenatmosphere in this embodiment. Alternatively, before the conductive film105 a and the conductive film 105 b are formed, RTA treatment at hightemperature for a short time may be performed in a manner similar tothat of the heat treatment performed on the oxide semiconductor film. Bythe heat treatment, the oxide semiconductor film 108 is heated whilebeing in contact with the silicon oxide film which forms the insulatingfilm 109. In addition, the resistance of the oxide semiconductor film108 is increased. Accordingly, electric characteristics of thetransistor can be improved and variation in the electric characteristicsthereof can be reduced. There is no particular limitation on when toperform this heat treatment as long as it is performed after theformation of the insulating film 109. When this heat treatment alsoserves as heat treatment in another step, for example, heat treatment information of a resin film or heat treatment for reducing resistance of atransparent conductive film, the number of steps can be prevented fromincreasing.

FIG. 2 is a top view of the semiconductor device illustrated in FIG. 1E.FIG. 1E is a cross-sectional view taken along dashed line A1-A2 in FIG.2.

A transistor 110 has the gate electrode 101; the gate insulating film102 over the gate electrode 101; the oxide semiconductor film 108 overthe gate insulating film 102; the source electrode 106 and the drainelectrode 107 over the oxide semiconductor film 108; and the insulatingfilm 109 over the source electrode 106, the drain electrode 107, and theoxide semiconductor film 108.

Next, after a conductive film is formed over the insulating film 109,the conductive film is patterned, so that a back gate electrode 111 maybe formed so as to overlap with the oxide semiconductor film 108 asillustrated in FIG. 3A. The back gate electrode 111 can be formed usinga material and a structure which are similar to those of the gateelectrode 101 or the source electrode 106 and the drain electrode 107.

The thickness of the back gate electrode 111 is 10 nm to 400 nm,preferably 100 nm to 200 nm. In this embodiment, a conductive film inwhich a titanium film, an aluminum film, and a titanium film aresequentially stacked is formed. Then, a resist mask is formed by aphotolithography method, an unnecessary portion is removed by etchingand the conductive film is processed (patterned) into a desired shape,whereby the back gate electrode 111 is formed.

Next, as illustrated in FIG. 3B, an insulating film 112 is formed so asto cover the back gate electrode 111. The insulating film 112 ispreferably formed using a material having a high barrier property whichcan prevent moisture, hydrogen, or the like in the atmosphere fromaffecting the characteristics of the transistor 110. For example, theinsulating film 112 can be formed to have a single layer or a stackedlayer using any of a silicon nitride film, a silicon nitride oxide film,an aluminum nitride film, an aluminum nitride oxide film, and the likeas an insulating film having a high barrier property with a plasmaenhanced CVD method, a sputtering method, or the like. The insulatingfilm 112 is preferably formed to have a thickness of, for example, 15 nmto 400 nm so as to obtain an effective barrier property.

In this embodiment, an insulating film is formed to have a thickness of300 nm with a plasma enhanced CVD method. The insulating film is formedunder the following conditions: the flow rate of silane gas is 4 sccm;the flow rate of dinitrogen monoxide (N₂O) is 800 sccm; and thesubstrate temperature is 400° C.

A top view of the semiconductor device illustrated in FIG. 3B isillustrated in FIG. 3C. FIG. 3B is a cross-sectional view taken alongdashed line A1-A2 in FIG. 3C.

Note that in FIG. 3B, the case is illustrated in which the back gateelectrode 111 covers the entire oxide semiconductor film 108; however,one embodiment of the present invention is not limited to thisstructure. The back gate electrode 111 may overlap with at least part ofthe channel formation region included in the oxide semiconductor film108.

The back gate electrode 111 may be in a floating state, that is,electrically isolated, or a state where a potential is applied. In thelatter state, to the back gate electrode 111, a potential which is thesame level as the gate electrode 101 may be applied, or a fixedpotential such as ground may be applied. The level of the potentialapplied to the back gate electrode 111 is controlled, so that thethreshold voltage of the transistor 110 can be controlled.

As in this embodiment, how characteristics of the transistor areinfluenced by high purification of the oxide semiconductor film byremoval of impurities such as hydrogen, water, or the like contained inthe oxide semiconductor film as much as possible will be described.

FIG. 27 is a cross-sectional view of an inverted staggered thin filmtransistor formed using an oxide semiconductor. An oxide semiconductorfilm (OS) is provided over a gate electrode (GE) with a gate insulatingfilm (GI) therebetween, and a source electrode (S) and a drain electrode(D) are provided thereover.

FIGS. 28A and 28B are energy band diagrams (schematic diagrams) of across-section taken along line A-A′ in FIG. 27. FIG. 28A illustrates thecase where voltages of the source electrode and the drain electrode areequal to each other (VD=0 V), and FIG. 28B illustrates the case where apositive potential (VD>0) is applied to the drain electrode with respectto the source electrode.

FIGS. 29A and 29B are energy band diagrams (schematic diagrams) of across-section taken along line B-B′ in FIG. 27. FIG. 29A illustrates astate where a positive potential (+VG) is applied to a gate electrode(GE) and an on state where carriers (electrons) flow between the sourceelectrode and the drain electrode. FIG. 29B illustrates a state where anegative potential (−VG) is applied to the gate electrode (GE) and anoff state (a minority carrier does not flow).

FIG. 30 illustrates a relation among a vacuum level, a work function(φ_(M)) of a metal and an electron affinity (χ) of an oxidesemiconductor.

Since a metal degenerates, a Fermi level (E_(F)) is located in aconduction band. On the other hand, in general, a conventional oxidesemiconductor is an n-type semiconductor, and the Fermi level (Ef)thereof is located nearer the conduction band (Ec) away from anintrinsic Fermi level (Ei) which is located in the center of the bandgap. Note that it is known that hydrogen in the oxide semiconductor is adonor and one of factors that makes the oxide semiconductor an n-typesemiconductor.

On the other hand, according to one embodiment of the present invention,when a metal whose electronegativity is lower than hydrogen is used forthe conductive film for the source electrode or the drain electrode,hydrogen which is an n-type impurity is removed from the oxidesemiconductor and the oxide semiconductor is highly purified so thatimpurities except a main component of the oxide semiconductor areincluded as little as possible in order that the oxide semiconductor maybe made to be an intrinsic (i-type) semiconductor. That is, the oxidesemiconductor becomes an i-type semiconductor not by addition ofimpurities but by removal of impurities such as hydrogen or water asmuch as possible to have high purity, so that an oxide semiconductorwhich is an intrinsic (i-type) semiconductor or is a substantiallyintrinsic (i-type) semiconductor is obtained. With the above structure,the Fermi level (Ef) can be substantially close to the same level as theintrinsic Fermi level (Ei), as indicated by arrows.

In general, the band gap (Eg) of the oxide semiconductor is 3.15 eV,electron affinity (χ) is 4.3 eV. The work function of titanium (Ti), bywhich the source electrode and the drain electrode are formed, isapproximately equal to the electron affinity (χ) of the oxidesemiconductor. In this case, at the interface between a metal and theoxide semiconductor, a Schottky barrier for electrons is not formed.

That is, in the case where the work function (φ_(M)) of a metal is equalto the electron affinity (χ) of the oxide semiconductor, an energy banddiagram (schematic diagram) is shown as illustrated in FIG. 28A when theoxide semiconductor and the source electrode or the drain electrode arein contact with each other.

In FIG. 28B, a black dot (●) indicates an electron, and when a positivepotential is applied to the drain electrode, the electron which crossesa barrier (h) is injected in the oxide semiconductor, and flows towardthe drain electrode. In this case, the height of the barrier (h) ischanged depending on gate voltage and drain voltage. When positive drainvoltage is applied, the height (h) of the barrier is smaller than theheight of the barrier of FIG. 28A without application of voltage, thatis ½ of the band gap (Eg).

At this time, the electron moves in the bottom, which is energeticallystable, on the oxide semiconductor side at the interface between thegate insulating film and the highly purified oxide semiconductor asillustrated in FIG. 29A.

In FIG. 29B, when a negative potential (reverse bias) is applied to thegate electrode (GE), holes which are minority carriers are substantiallyzero; therefore, current is substantially close to zero.

For example, even when the channel width W of a thin film transistor is1×10⁴ lam and the channel length thereof is 3 μm, an off-state currentof less than or equal to 10⁻¹³ A and a subthreshold swing (S value) of0.1 V/dec. (gate insulating film having a thickness of 100 nm) can beobtained.

In this manner, the oxide semiconductor film is highly purified so thatimpurities such as water or hydrogen except a main component of theoxide semiconductor are contained as little as possible, whereby theoperation of the thin film transistor can be favorable.

Embodiment 2

A method for manufacturing a semiconductor device will be described withreference to FIGS. 4A to 4D using a bottom gate thin film transistorhaving a channel etched structure as an example.

First, as illustrated in FIG. 4A, in accordance with the manufacturingmethod described in Embodiment 1, over the island-shaped oxidesemiconductor film 104, the conductive film 105 a is formed using ametal material which has low contact resistance to the oxidesemiconductor film 104, such as titanium, tungsten, or molybdenum, andthereover, the conductive film 105 b is formed using a lowelectronegativity metal, a low electronegativity metal compound, or alow electronegativity alloy. Since the kind of material, the structure,and the range of the thickness of the conductive film 105 a and theconductive film 105 b are already described in Embodiment 1, descriptionis omitted here. In this embodiment, a titanium film having a thicknessof 100 nm formed with a sputtering method is used as the conductive film105 a, and an aluminum film having a thickness of 200 nm formed with asputtering method is used as the conductive film 105 b.

After the conductive film 105 a and the conductive film 105 b areformed, the exposed conductive film 105 b may be subjected to heattreatment in a reduced atmosphere or an inert gas atmosphere such as anitrogen atmosphere or a rare gas (argon, helium, or the like)atmosphere. The temperature range of the heat treatment is 200° C. to450° C. as in Embodiment 1.

Next, as illustrated in FIG. 4B, the conductive film 105 b is removed byetching or the like. The etching is preferably wet etching so as toprevent the conductive film 105 a from being etched. Specifically, inthis embodiment, since the aluminum film is used for the conductive film105 b, wet etching is performed using the solution containing phosphoricacid, for example, an Al-Etchant (an aqueous solution containing nitricacid of 2.0 wt %, acetic acid of 9.8 wt %, and phosphoric acid of 72.3wt %) produced by Wako Pure Chemical Industries Co., Ltd, whereby theconductive film 105 b is removed. Note that when the conductive film 105b is removed using dry etching, a gas containing chlorine (Cl₂), boronchloride (BCl₃), or the like may be used. Note that in the case wheredry etching is performed, since there is no difference in selectivitybetween the conductive film 105 a which is the titanium film and theconductive film 105 b which is the aluminum film, the time of dryetching may be controlled at the time of etching so that the conductivefilm 105 a may remain.

Impurities such as moisture or hydrogen existing in the oxidesemiconductor film 104, the gate insulating film 102, or at theinterface between the oxide semiconductor film 104 and anotherinsulating film and the vicinity thereof can be occluded or adsorbed bythe conductive film 105 b. Therefore, the conductive film 105 b isremoved, so that the impurities such as moisture or hydrogen occluded oradsorbed by the conductive film 105 b can also be removed.

Next, as illustrated in FIG. 4C, a conductive film 105 c is formed usinga low electronegativity metal, a low electronegativity metal compound,or a low electronegativity alloy over the conductive film 105 a. Thekind of material and the range of the thickness of the conductive film105 c are the same as those of the conductive film 105 b. In thisembodiment, an aluminum film having a thickness of 200 nm formed with asputtering method is used as the conductive film 105 c.

In one embodiment of the present invention, after the conductive film105 b is removed, the conductive film 105 c is formed using a lowelectronegativity metal, a low electronegativity metal compound, or alow electronegativity alloy. The conductive film 105 c easily occludesor adsorbs impurities such as moisture or hydrogen, as compared to theconductive film 105 b which has already occluded or adsorbed impurities.Therefore, the impurities existing in the oxide semiconductor film 104,the gate insulating film 102, or at the interface between the oxidesemiconductor film 104 and another insulating film and the vicinitythereof can be further reduced, as compared to the case of Embodiment 1.Therefore, by elimination of impurities such as moisture or hydrogen,the oxide semiconductor film 104 which is an intrinsic (i-type)semiconductor or a substantially i-type semiconductor can be obtained,and deterioration of characteristics of the transistor due to theimpurities, such as shifts in threshold voltage, can be prevented frombeing promoted and off-state current can be reduced.

After the conductive film 105 c is formed, the exposed conductive film105 c may be subjected to heat treatment again in a reduced atmosphereor an inert gas atmosphere such as a nitrogen atmosphere or a rare gas(argon, helium, or the like) atmosphere. The temperature range of theheat treatment is 200° C. to 450° C. as in Embodiment 1. The heattreatment is performed, so that impurities such as moisture or hydrogenexisting in the oxide semiconductor film 104, the gate insulating film102, or at the interface between the oxide semiconductor film 104 andanother insulating film and the vicinity thereof can be easily occludedor adsorbed by the conductive film 105 c.

Next, as illustrated in FIG. 4D, the conductive film 105 a and theconductive film 105 c are processed (patterned) into desired shapes byetching or the like, whereby a source electrode 126 and a drainelectrode 127 are formed. For example, when a titanium film is used forthe conductive film 105 a and an aluminum film is used for theconductive film 105 c, after wet etching is performed on the conductivefilm 105 c using a solution containing phosphoric acid, wet etching maybe performed on the conductive film 105 a using a solution (ammoniaperoxide mixture) containing ammonia and oxygenated water. Specifically,in this embodiment, an Al-Etchant (an aqueous solution containing nitricacid of 2.0 wt %, acetic acid of 9.8 wt %, and phosphoric acid of 72.3wt %) produced by Wako Pure Chemical Industries, Ltd. is used as thesolution containing phosphoric acid. In addition, as the ammoniaperoxide mixture, specifically, a solution in which oxygenated water of31 wt %, ammonia water of 28 wt %, and water are mixed at a volume ratioof 5:2:2 is used. Alternatively, dry etching may be performed on theconductive film 105 a and the conductive film 105 c using a gascontaining chlorine (Cl₂), boron chloride (BCl₃), or the like.

When the source electrode 126 and the drain electrode 127 are formed bythe patterning, part of an exposed portion of the island-shaped oxidesemiconductor film 104 is etched, so that a groove (a depressed portion)is formed in some cases. In this embodiment, the case in which anisland-shaped oxide semiconductor film 128 having a groove (a depressedportion) is formed by the etching is described. The conductive film 105a serving as part of the source electrode 126 and the drain electrode127 is in contact with the oxide semiconductor film 128. In addition,since the conductive film 105 a is formed using a metal material havinglow contact resistance to the oxide semiconductor film 128 as describedabove, contact resistance between the source electrode 126 or the drainelectrode 127 and the oxide semiconductor film 128 is reduced.Accordingly, on-state current and field-effect mobility of the TFT canbe increased.

Then, after the source electrode 126 and the drain electrode 127 areformed, an insulating film 129 is formed so as to cover the sourceelectrode 126, the drain electrode 127, and the oxide semiconductor film128. The kind of material, the structure, and the range of the thicknessof the insulating film 129 are the same as those of the insulating film109 described in Embodiment 1. In this embodiment, the insulating film129 having a structure in which a silicon nitride film having athickness of 100 nm formed with a sputtering method is stacked over asilicon oxide film having a thickness of 200 nm formed with a sputteringmethod is formed. The substrate temperature in film formation may behigher than or equal to room temperature and lower than or equal to 300°C. and in this embodiment, is 100° C.

An exposed region of the oxide semiconductor film 128 provided betweenthe source electrode 126 and the drain electrode 127 and the siliconoxide film which forms the insulating film 129 are provided in contactwith each other, so that resistance of the region of the oxidesemiconductor film 128 which is in contact with the insulating film 129is increased (carrier concentration is decreased, preferably, less than1×10¹⁸/cm³), whereby the oxide semiconductor film 128 having a channelformation region with high resistance can be formed.

Note that after the insulating film 129 is formed, heat treatment may beperformed. As for the condition of the heat treatment, the condition ofthe heat treatment which is performed after the insulating film 109 isformed in Embodiment 1 may be referred to.

A thin film transistor 120 formed in accordance with the manufacturingmethod has the gate electrode 101; the gate insulating film 102 over thegate electrode 101; the oxide semiconductor film 128 over the gateinsulating film 102; the source electrode 126 and the drain electrode127 over the oxide semiconductor film 128; and the insulating film 129over the source electrode 126, the drain electrode 127, and the oxidesemiconductor film 128.

Next, after a conductive film is formed over the insulating film 129,the conductive film is patterned, so that a back gate electrode may beformed so as to overlap with the oxide semiconductor film 128. Since thekind of material, the structure, and the range of the thickness of theback gate electrode are similar to those of the back gate electrode 111described in Embodiment 1, description is omitted here.

When the back gate electrode is formed, an insulating film is formed soas to cover the back gate electrode. Since the kind of material, thestructure, and the range of the thickness of the insulating film whichcovers the back gate electrode are similar to those of the insulatingfilm 112 described in Embodiment 1, description is omitted here.

This embodiment can be implemented by being combined as appropriate withany of the above-described embodiments.

Embodiment 3

A method for manufacturing a semiconductor device will be described withreference to FIGS. 5A to 5D using a bottom gate thin film transistorhaving a channel etched structure as an example.

First, as illustrated in FIG. 5A, in accordance with the manufacturingmethod described in Embodiment 1, over the island-shaped oxidesemiconductor film 104, the conductive film 105 a is formed using ametal material which has low contact resistance to the oxidesemiconductor film 104, such as titanium, tungsten, or molybdenum, andthereover, the conductive film 105 b is formed using a lowelectronegativity metal, a low electronegativity metal compound, or alow electronegativity alloy. Since the kind of material, the structure,and the range of the thickness of the conductive film 105 a and theconductive film 105 b are already described in Embodiment 1, descriptionis omitted here. In this embodiment, a titanium film having a thicknessof 100 nm formed with a sputtering method is used as the conductive film105 a, and an aluminum film having a thickness of 200 nm formed with asputtering method is used as the conductive film 105 b.

After the conductive film 105 a and the conductive film 105 b areformed, the exposed conductive film 105 b may be subjected to heattreatment in a reduced atmosphere or an inert gas atmosphere such as anitrogen atmosphere or a rare gas (argon, helium, or the like)atmosphere. The temperature range of the heat treatment is 200° C. to450° C. as in Embodiment 1.

Next, as illustrated in FIG. 5B, the conductive film 105 b is removed byetching or the like. The etching is preferably wet etching so as toprevent the conductive film 105 a from being etched. Specifically, inthis embodiment, since the aluminum film is used for the conductive film105 b, wet etching is performed using the solution containing phosphoricacid, for example, an Al-Etchant (an aqueous solution containing nitricacid of 2.0 wt %, acetic acid of 9.8 wt %, and phosphoric acid of 72.3wt %) produced by Wako Pure Chemical Industries Co., Ltd, whereby theconductive film 105 b is removed. Note that when the conductive film 105b is removed using dry etching, a gas containing chlorine (Cl₂), boronchloride (BCl₃), or the like may be used. Note that in the case wheredry etching is performed, since there is no difference in selectivitybetween the conductive film 105 a which is the titanium film and theconductive film 105 b which is the aluminum film, the time of dryetching may be controlled at the time of etching so that the conductivefilm 105 a may remain.

Impurities such as moisture or hydrogen existing in the oxidesemiconductor film 104, the gate insulating film 102, or at theinterface between the oxide semiconductor film 104 and anotherinsulating film and the vicinity thereof can be occluded or adsorbed bythe conductive film 105 b. Therefore, the conductive film 105 b isremoved, so that the impurities such as moisture or hydrogen occluded oradsorbed by the conductive film 105 b can also be removed.

Next, as illustrated in FIG. 5C, the conductive film 105 c is formedusing a low electronegativity metal, a low electronegativity metalcompound, or a low electronegativity alloy over the conductive film 105a and a conductive film 105 d is formed using a metal material which canprevent oxidation of the conductive film 105 c, such as titanium,tungsten, or molybdenum. The kind of material and the range of thethickness of the conductive film 105 c are the same as those of theconductive film 105 b. The thickness of the conductive film 105 d ispreferably 10 nm to 200 nm, more preferably, 50 nm to 150 nm. In thisembodiment, an aluminum film having a thickness of 200 nm formed with asputtering method is used as the conductive film 105 c, and a titaniumfilm having a thickness of 100 nm formed with a sputtering method isused as the conductive film 105 d.

In one embodiment of the present invention, after the conductive film105 b is removed, the conductive film 105 c is additionally formed usinga low electronegativity metal, a low electronegativity metal compound,or a low electronegativity alloy. The conductive film 105 c easilyoccludes or adsorbs impurities such as moisture or hydrogen, as comparedto the conductive film 105 b which has already occluded or adsorbedimpurities. Therefore, the impurities existing in the oxidesemiconductor film 104, the gate insulating film 102, or at theinterface between the oxide semiconductor film 104 and anotherinsulating film and the vicinity thereof can be further reduced, ascompared to the case of Embodiment 1. Therefore, by elimination ofimpurities such as moisture or hydrogen, the oxide semiconductor film104 which is an intrinsic (i-type) semiconductor or a substantiallyi-type semiconductor can be obtained, and deterioration ofcharacteristics of the transistor due to the impurities, such as shiftsin threshold voltage, can be prevented from being promoted and off-statecurrent can be reduced.

After the conductive film 105 d is formed, the exposed conductive film105 d may be subjected to heat treatment in a reduced atmosphere or aninert gas atmosphere such as a nitrogen atmosphere or a rare gas (argon,helium, or the like) atmosphere. The temperature range of the heattreatment is 200° C. to 450° C. as in Embodiment 1. The heat treatmentis performed, so that impurities such as moisture or hydrogen existingin the oxide semiconductor film 104, the gate insulating film 102, or atthe interface between the oxide semiconductor film 104 and anotherinsulating film and the vicinity thereof can be easily occluded oradsorbed by the conductive film 105 c.

Next, as illustrated in FIG. 5D, the conductive film 105 a, theconductive film 105 c, and the conductive film 105 d are processed(patterned) into desired shapes by etching or the like, whereby a sourceelectrode 136 and a drain electrode 137 are formed. For example, when atitanium film is used for the conductive film 105 a, an aluminum film isused for the conductive film 105 c, and a titanium film is used for theconductive film 105 d, after wet etching is performed on the conductivefilm 105 d using a solution (ammonia peroxide mixture) containingammonia and oxygenated water, wet etching may be performed on theconductive film 105 c using a solution containing phosphoric acid, andthen wet etching may be performed on the conductive film 105 a using asolution (ammonia peroxide mixture) containing ammonia and oxygenatedwater. Specifically, in this embodiment, an Al-Etchant (an aqueoussolution containing nitric acid of 2.0 wt %, acetic acid of 9.8 wt %,and phosphoric acid of 72.3 wt %) produced by Wako Pure ChemicalIndustries, Ltd. is used as the solution containing phosphoric acid. Inaddition, as the ammonia peroxide mixture, specifically, a solution inwhich oxygenated water of 31 wt %, ammonia water of 28 wt %, and waterare mixed at a volume ratio of 5:2:2 is used. Alternatively, dry etchingmay be performed on the conductive film 105 a, the conductive film 105c, and the conductive film 105 d using a gas containing chlorine (Cl₂),boron chloride (BCl₃), or the like.

When the source electrode 136 and the drain electrode 137 are formed bythe patterning, part of an exposed portion of the island-shaped oxidesemiconductor film 104 is etched, so that a groove (a depressed portion)is formed in some cases. In this embodiment, the case in which anisland-shaped oxide semiconductor film 138 having a groove (a depressedportion) is formed by the etching is described. The conductive film 105a serving as part of the source electrode 136 and the drain electrode137 is in contact with the oxide semiconductor film 138. In addition,since the conductive film 105 a is formed using a metal material havinglow contact resistance to the oxide semiconductor film as describedabove, contact resistance between the source electrode 136 or the drainelectrode 137 and the oxide semiconductor film 138 is reduced.Accordingly, on-state current and field-effect mobility of the TFT canbe increased.

Then, after the source electrode 136 and the drain electrode 137 areformed, an insulating film 139 is formed so as to cover the sourceelectrode 136, the drain electrode 137, and the oxide semiconductor film138. The kind of material, the structure, and the range of the thicknessof the insulating film 139 are the same as those of the insulating film109 described in Embodiment 1. In this embodiment, the insulating film139 having a structure in which a silicon nitride film having athickness of 100 nm formed with a sputtering method is stacked over asilicon oxide film having a thickness of 200 nm formed with a sputteringmethod is formed. The substrate temperature in film formation may behigher than or equal to room temperature and lower than or equal to 300°C. and in this embodiment, is 100° C.

An exposed region of the oxide semiconductor film 138 provided betweenthe source electrode 136 and the drain electrode 137 and the siliconoxide film which forms the insulating film 139 are provided in contactwith each other, so that oxygen is supplied to the region of the oxidesemiconductor film 138 which is in contact with the insulating film 139,and the resistance of the region is increased (carrier concentration isdecreased, preferably, less than 1×10¹⁸/cm³), whereby the oxidesemiconductor film 138 having a channel formation region with highresistance can be formed.

Note that after the insulating film 139 is formed, heat treatment may beperformed. As for the condition of the heat treatment, the condition ofthe heat treatment which is performed after the insulating film 109 isformed in Embodiment 1 may be referred to.

A thin film transistor 130 formed in accordance with the manufacturingmethod has the gate electrode 101; the gate insulating film 102 over thegate electrode 101; the oxide semiconductor film 138 over the gateinsulating film 102; the source electrode 136 and the drain electrode137 over the oxide semiconductor film 138; and the insulating film 139over the source electrode 136, the drain electrode 137, and the oxidesemiconductor film 138.

Next, after a conductive film is formed over the insulating film 139,the conductive film is patterned, so that a back gate electrode may beformed so as to overlap with the oxide semiconductor film 138. Since thekind of material, the structure, and the range of the thickness of theback gate electrode are similar to those of the back gate electrode 111described in Embodiment 1, description is omitted here.

When the back gate electrode is formed, an insulating film is formed soas to cover the back gate electrode. Since the kind of material, thestructure, and the range of the thickness of the insulating film whichcovers the back gate electrode are similar to those of the insulatingfilm 112 described in Embodiment 1, description is omitted here.

This embodiment can be implemented by being combined as appropriate withany of the above-described embodiments.

Embodiment 4

A method for manufacturing a semiconductor device will be described withreference to FIGS. 6A to 6D using a bottom gate thin film transistorhaving a channel etched structure as an example.

First, as illustrated in FIG. 6A, in accordance with the manufacturingmethod described in Embodiment 1, over the island-shaped oxidesemiconductor film 104, the conductive film 105 a is formed using ametal material which has low contact resistance to the oxidesemiconductor film 104, such as titanium, tungsten, or molybdenum, andthereover, the conductive film 105 b is formed using a lowelectronegativity metal, a low electronegativity metal compound, or alow electronegativity alloy. Since the kind of material, the structure,and the range of the thickness of the conductive film 105 a and theconductive film 105 b are already described in Embodiment 1, descriptionis omitted here. In this embodiment, a titanium film having a thicknessof 100 nm formed with a sputtering method is used as the conductive film105 a, and an aluminum film having a thickness of 200 nm formed with asputtering method is used as the conductive film 105 b.

After the conductive film 105 a and the conductive film 105 b areformed, the exposed conductive film 105 b may be subjected to heattreatment in a reduced atmosphere or an inert gas atmosphere such as anitrogen atmosphere or a rare gas (argon, helium, or the like)atmosphere. The temperature range of the heat treatment is 200° C. to450° C. as in Embodiment 1.

Next, as illustrated in FIG. 6B, the conductive film 105 b is removed byetching or the like. The etching is preferably wet etching so as toprevent the conductive film 105 a from being etched. Specifically, inthis embodiment, since the aluminum film is used for the conductive film105 b, wet etching is performed using the solution containing phosphoricacid, for example, an Al-Etchant (an aqueous solution containing nitricacid of 2.0 wt %, acetic acid of 9.8 wt %, and phosphoric acid of 72.3wt %) produced by Wako Pure Chemical Industries Co., Ltd, whereby theconductive film 105 b is removed. Note that when the conductive film 105b is removed using dry etching, a gas containing chlorine (Cl₂), boronchloride (BCl₃), or the like may be used. Note that in the case wheredry etching is performed, since there is no difference in selectivitybetween the conductive film 105 a which is the titanium film and theconductive film 105 b which is the aluminum film, the time of dryetching may be controlled at the time of etching so that the conductivefilm 105 a may remain.

Impurities such as moisture or hydrogen existing in the oxidesemiconductor film 104, the gate insulating film 102, or at theinterface between the oxide semiconductor film 104 and anotherinsulating film and the vicinity thereof can be occluded or adsorbed bythe conductive film 105 b. Therefore, the conductive film 105 b isremoved, so that the impurities such as moisture or hydrogen occluded oradsorbed by the conductive film 105 b can also be removed.

Next, as illustrated in FIG. 6C, a conductive film 105 e formed using ametal material which has low contact resistance to the oxidesemiconductor film 104, such as titanium, tungsten, or molybdenum, theconductive film 105 c formed using a low electronegativity metal, a lowelectronegativity metal compound, or a low electronegativity alloy, andthe conductive film 105 d formed using a metal material which canprevent oxidation of the conductive film 105 c, such as titanium,tungsten, or molybdenum are additionally formed over the conductive film105 a. The range of the thickness of the conductive film 105 e and theconductive film 105 d is the same as that of the conductive film 105 a.The kind of material and the range of the thickness of the conductivefilm 105 c are the same as those of the conductive film 105 b. In thisembodiment, an aluminum film having a thickness of 200 nm formed with asputtering method is used as the conductive film 105 c, a titanium filmhaving a thickness of 100 nm formed with a sputtering method is used asthe conductive film 105 d, and a titanium film having a thickness of 100nm formed with a sputtering method is used as the conductive film 105 e.

In one embodiment of the present invention, after the conductive film105 b is removed, the conductive film 105 c is additionally formed usinga low electronegativity metal, a low electronegativity metal compound,or a low electronegativity alloy. The conductive film 105 c easilyoccludes or adsorbs impurities such as moisture or hydrogen, as comparedto the conductive film 105 b which has already occluded or adsorbedimpurities. Therefore, the impurities existing in the oxidesemiconductor film 104, the gate insulating film 102, or at theinterface between the oxide semiconductor film 104 and anotherinsulating film and the vicinity thereof can be further reduced, ascompared to the case of Embodiment 1. Therefore, by elimination ofimpurities such as moisture or hydrogen, the oxide semiconductor film104 which is an intrinsic (i-type) semiconductor or a substantiallyi-type semiconductor can be obtained, and deterioration ofcharacteristics of the transistor due to the impurities, such as shiftsin threshold voltage, can be prevented from being promoted and off-statecurrent can be reduced.

After the conductive film 105 d is formed, the exposed conductive film105 d may be subjected to heat treatment again in a reduced atmosphereor an inert gas atmosphere such as a nitrogen atmosphere or a rare gas(argon, helium, or the like) atmosphere. The temperature range of theheat treatment is 200° C. to 450° C. as in Embodiment 1. The heattreatment is performed, so that impurities such as moisture or hydrogenexisting in the oxide semiconductor film 104, the gate insulating film102, or at the interface between the oxide semiconductor film 104 andanother insulating film and the vicinity thereof can be easily occludedor adsorbed by the conductive film 105 c.

Next, as illustrated in FIG. 6D, the conductive film 105 a, theconductive film 105 c, the conductive film 105 d, and the conductivefilm 105 e are processed (patterned) into desired shapes by etching orthe like, whereby a source electrode 146 and a drain electrode 147 areformed. For example, when a titanium film is used for the conductivefilm 105 a, an aluminum film is used for the conductive film 105 c, atitanium film is used for the conductive film 105 d, and a titanium filmis used for the conductive film 105 e, after wet etching is performed onthe conductive film 105 d using a solution (ammonia peroxide mixture)containing ammonia and oxygenated water, wet etching may be performed onthe conductive film 105 c using a solution containing phosphoric acid,and then wet etching may be performed on the conductive film 105 e andthe conductive film 105 a using a solution (ammonia peroxide mixture)containing ammonia and oxygenated water. Specifically, in thisembodiment, an Al-Etchant (an aqueous solution containing nitric acid of2.0 wt %, acetic acid of 9.8 wt %, and phosphoric acid of 72.3 wt %)produced by Wako Pure Chemical Industries, Ltd. is used as the solutioncontaining phosphoric acid. In addition, as the ammonia peroxidemixture, specifically, a solution in which oxygenated water of 31 wt %,ammonia water of 28 wt %, and water are mixed at a volume ratio of 5:2:2is used. Alternatively, dry etching may be performed on the conductivefilm 105 a, the conductive film 105 c, the conductive film 105 d, andthe conductive film 105 e using a gas containing chlorine (Cl₂), boronchloride (BCl₃), or the like.

When the source electrode 146 and the drain electrode 147 are formed bythe patterning, part of an exposed portion of the island-shaped oxidesemiconductor film 104 is etched, so that a groove (a depressed portion)is formed in some cases. In this embodiment, the case in which anisland-shaped oxide semiconductor film 148 having a groove (a depressedportion) is formed by the etching is described. The conductive film 105a serving as part of the source electrode 146 and the drain electrode147 is in contact with the oxide semiconductor film 148. In addition,since the conductive film 105 a is formed using a metal material havinglow contact resistance to the oxide semiconductor film 148 as describedabove, contact resistance between the source electrode 146 or the drainelectrode 147 and the oxide semiconductor film 148 is reduced.Accordingly, on-state current and field-effect mobility of the TFT canbe increased.

Then, after the source electrode 146 and the drain electrode 147 areformed, an insulating film 149 is formed so as to cover the sourceelectrode 146, the drain electrode 147, and the oxide semiconductor film148. The kind of material, the structure, and the range of the thicknessof the insulating film 149 are the same as those of the insulating film109 described in Embodiment 1. In this embodiment, the insulating film149 having a structure in which a silicon nitride film having athickness of 100 nm formed with a sputtering method is stacked over asilicon oxide film having a thickness of 200 nm formed with a sputteringmethod is formed. The substrate temperature in film formation may behigher than or equal to room temperature and lower than or equal to 300°C. and in this embodiment, is 100° C.

An exposed region of the oxide semiconductor film 148 provided betweenthe source electrode 146 and the drain electrode 147 and the siliconoxide film which forms the insulating film 149 are provided in contactwith each other, so that oxygen is supplied to the region of the oxidesemiconductor film 148 which is in contact with the insulating film 149,and the resistance of the region is increased (carrier concentration isdecreased, preferably, less than 1×10¹⁸/cm³), whereby the oxidesemiconductor film 148 having a channel formation region with highresistance can be formed.

After the insulating film 149 is formed, heat treatment may beperformed. As for the condition of the heat treatment, the condition ofthe heat treatment which is performed after the insulating film 109 isformed in Embodiment 1 may be referred to.

A thin film transistor 140 formed in accordance with the manufacturingmethod has the gate electrode 101; the gate insulating film 102 over thegate electrode 101; the oxide semiconductor film 148 over the gateinsulating film 102; the source electrode 146 and the drain electrode147 over the oxide semiconductor film 148; and the insulating film 149over the source electrode 146, the drain electrode 147, and the oxidesemiconductor film 148.

Next, after a conductive film is formed over the insulating film 149,the conductive film is patterned, so that a back gate electrode may beformed so as to overlap with the oxide semiconductor film 148. Since thekind of material, the structure, and the range of the thickness of theback gate electrode are similar to those of the back gate electrode 111described in Embodiment 1, description is omitted here.

When the back gate electrode is formed, an insulating film is formed soas to cover the back gate electrode. Since the kind of material, thestructure, and the range of the thickness of the insulating film whichcovers the back gate electrode are similar to those of the insulatingfilm 112 described in Embodiment 1, description is omitted here.

This embodiment can be implemented by being combined as appropriate withany of the above-described embodiments.

Embodiment 5

In this embodiment, a method for manufacturing a semiconductor devicewill be described with reference to FIGS. 7A to 7E, FIG. 8, and FIGS. 9Ato 9C using a bottom gate thin film transistor having a channelprotective structure as an example. Note that the same portions asEmbodiment 1 or portions having functions similar to those of Embodiment1 can be formed as in Embodiment 1, and also the same steps asEmbodiment 1 or the steps similar to those of Embodiment 1 can beperformed in a manner similar to those of Embodiment 1; therefore,repetitive description thereof is omitted.

As illustrated in FIG. 7A, a gate electrode 301 is formed over asubstrate 300 having an insulating surface. An insulating film servingas a base film may be provided between the substrate 300 and the gateelectrode 301. The descriptions of the material, the structure, and thethickness of the gate electrode 101 in Embodiment 1 may be referred tofor the material, the structure, and the thickness of the gate electrode301. The descriptions of the material, the structure, and the thicknessof the base film in Embodiment 1 may be referred to for the material,the structure, and the thickness of the base film.

Next, a gate insulating film 302 is formed over the gate electrode 301.The descriptions of the material, the thickness, the structure, and themanufacturing method of the gate insulating film 102 in Embodiment 1 maybe referred to for the material, the thickness, the structure, and themanufacturing method of the gate insulating film 302.

Next, an oxide semiconductor film 303 is formed over the gate insulatingfilm 302. The descriptions of the material, the thickness, thestructure, and the manufacturing method of the oxide semiconductor film103 in Embodiment 1 may be referred to for the material, the thickness,the structure, and the manufacturing method of the island-shaped oxidesemiconductor film 303.

Next, heat treatment is performed on the oxide semiconductor film 303 ina reduced atmosphere, an inert gas atmosphere such as a nitrogenatmosphere or a rare gas atmosphere, an oxygen gas atmosphere, or anultra dry air atmosphere (in air whose moisture content is less than orequal to 20 ppm (dew point conversion, −55° C.), preferably, less thanor equal to 1 ppm, more preferably, less than or equal to 10 ppb in thecase where measurement is performed using a dew-point meter of a cavityring-down laser spectroscopy (CRDS) system). The descriptions of theheat treatment performed on the oxide semiconductor film 103 inEmbodiment 1 may be referred to for the heat treatment performed on theoxide semiconductor film 303. The oxide semiconductor film 303 issubjected to heat treatment in the above atmosphere, so that anisland-shaped oxide semiconductor film 304 in which moisture or hydrogencontained in the oxide semiconductor film 303 is eliminated is formed asillustrated in FIG. 7B. Impurities such as moisture or hydrogen areeliminated by the heat treatment, and the island-shaped oxidesemiconductor film 304 is an intrinsic (i-type) semiconductor or asubstantially i-type semiconductor; therefore, deterioration ofcharacteristics of the transistor due to the impurities, such as shiftsin threshold voltage, can be prevented from being promoted and off-statecurrent can be reduced.

Next, as illustrated in FIG. 7C, a channel protective film 311 is formedover the oxide semiconductor film 304 so as to overlap with a portion ofthe oxide semiconductor film 304, which serves as a channel formationregion. The channel protective film 311 can prevent the portion of theoxide semiconductor film 304, which serves as a channel formationregion, from being damaged in a later step (for example, reduction inthickness due to plasma or an etchant in etching). Therefore,reliability of the thin film transistor can be improved.

The channel protective film 311 can be formed using an inorganicmaterial including oxygen (such as silicon oxide, silicon oxynitride, orsilicon nitride oxide). The channel protective film 311 can be formed bya vapor deposition method such as a plasma enhanced CVD method or athermal CVD method, or a sputtering method. After the formation of thechannel protective film 311, the shape thereof is processed by etching.Here, the channel protective film 311 is formed in such a manner that asilicon oxide film is formed with a sputtering method and processed byetching using a mask formed by photolithography.

When the channel protective film 311 which is an insulating film such asa silicon oxide film or a silicon oxynitride film is formed with asputtering method, a PCVD method, or the like so as to be in contactwith the island-shaped oxide semiconductor film 304, oxygen is suppliedto at least a region of the island-shaped oxide semiconductor film 304,which is in contact with the channel protective film 311, and theresistance of the region is increased because carrier concentration ispreferably decreased to less than 1×10¹⁸/cm³, more preferably, less thanor equal to 1×10¹⁴/cm³, whereby a high-resistance oxide semiconductorregion is formed. By the formation of the channel protective film 311,the oxide semiconductor film 304 can have the high-resistance oxidesemiconductor region in the vicinity of the interface between thechannel protective film 311 and the oxide semiconductor film 304.

Next, over the island-shaped oxide semiconductor film 304, a conductivefilm 305 a formed using a metal material which has low contactresistance to the oxide semiconductor film 304, such as titanium,tungsten, or molybdenum, and a conductive film 305 b formed using a lowelectronegativity metal, a low electronegativity metal compound, or alow electronegativity alloy are sequentially formed. The descriptions ofthe kind of the material, the structure, and the thickness of theconductive film 105 a and the conductive film 105 b in Embodiment 1 maybe referred to for the kind of the material, the structure, and thethickness of the conductive film 305 a and the conductive film 305 b. Inthis embodiment, a titanium film having a thickness of 100 nm formedwith a sputtering method is used as the conductive film 305 a, and analuminum film having a thickness of 200 nm formed with a sputteringmethod is used as the conductive film 305 b.

In one embodiment of the present invention, the conductive film 305 b isformed using a low electronegativity metal, a low electronegativitymetal compound, or a low electronegativity alloy, so that impuritiessuch as moisture or hydrogen existing in the oxide semiconductor film304, the gate insulating film 302, or at an interface between the oxidesemiconductor film 304 and another insulating film and the vicinitythereof are occluded or adsorbed by the conductive film 305 b.Therefore, by elimination of impurities such as moisture or hydrogen,the oxide semiconductor film 304 which is an intrinsic (i-type)semiconductor or a substantially i-type semiconductor can be obtained,and deterioration of characteristics of the transistor due to theimpurities, such as shifts in threshold voltage, can be prevented frombeing promoted and off-state current can be reduced.

After the conductive film 305 a and the conductive film 305 b areformed, the exposed conductive film 305 b may be subjected to heattreatment in a reduced atmosphere or an inert gas atmosphere such as anitrogen atmosphere or a rare gas (argon, helium, or the like)atmosphere. The temperature range of the heat treatment is 200° C. to450° C. as in Embodiment 1.

Next, as illustrated in FIG. 7D, the conductive film 305 a and theconductive film 305 b are processed (patterned) into desired shapes byetching or the like, whereby a source electrode 306 and a drainelectrode 307 are formed. For example, when a titanium film is used forthe conductive film 305 a and an aluminum film is used for theconductive film 305 b, after wet etching is performed on the conductivefilm 305 b using a solution containing phosphoric acid, wet etching maybe performed on the conductive film 305 a using a solution (ammoniaperoxide mixture) containing ammonia and oxygenated water. Specifically,in this embodiment, an Al-Etchant (an aqueous solution containing nitricacid of 2.0 wt %, acetic acid of 9.8 wt %, and phosphoric acid of 72.3wt %) produced by Wako Pure Chemical Industries, Ltd. is used as thesolution containing phosphoric acid. In addition, as the ammoniaperoxide mixture, specifically, a solution in which oxygenated water of31 wt %, ammonia water of 28 wt %, and water are mixed at a volume ratioof 5:2:2 is used. Alternatively, dry etching may be performed on theconductive film 305 a and the conductive film 305 b using a gascontaining chlorine (Cl₂), boron chloride (BCl₃), or the like.

The conductive film 305 a serving as part of the source electrode 306and the drain electrode 307 is in contact with the oxide semiconductorfilm 304. In addition, since the conductive film 305 a is formed using ametal material having low contact resistance to the oxide semiconductorfilm as described above, contact resistance between the source electrode306 or the drain electrode 307 and the oxide semiconductor film 304 isreduced. Accordingly, on-state current and field-effect mobility of theTFT can be increased.

Then, as illustrated in FIG. 7E, after the source electrode 306 and thedrain electrode 307 are formed, an insulating film 309 is formed so asto cover the oxide semiconductor film 304, the source electrode 306, thedrain electrode 307, and the channel protective film 311. The kind ofmaterial, the structure, and the range of the thickness of theinsulating film 309 are the same as those of the insulating film 109described in Embodiment 1. In this embodiment, the insulating film 309having a structure in which a silicon nitride film having a thickness of100 nm formed with a sputtering method is stacked over a silicon oxidefilm having a thickness of 200 nm formed with a sputtering method isformed. The substrate temperature in film formation may be higher thanor equal to room temperature and lower than or equal to 300° C. and inthis embodiment, is 100° C.

Note that after the insulating film 309 is formed, heat treatment may beperformed. As for the condition of the heat treatment, the condition ofthe heat treatment which is performed after the insulating film 109 isformed in Embodiment 1 may be referred to.

A top view of the semiconductor device illustrated in FIG. 7E isillustrated in FIG. 8. FIG. 7E is a cross-sectional view taken alongdashed line C1-C2 in FIG. 8.

A thin film transistor 310 formed in accordance with the manufacturingmethod has the gate electrode 301; the gate insulating film 302 over thegate electrode 301; the oxide semiconductor film 304 over the gateinsulating film 302; the channel protective film 311 over the oxidesemiconductor film 304; the source electrode 306 and the drain electrode307 over the oxide semiconductor film 304; and the insulating film 309over the oxide semiconductor film 304, the source electrode 306, thedrain electrode 307, and the channel protective film 311.

Next, as illustrated in FIG. 9A, after a conductive film is formed overthe insulating film 309, the conductive film is patterned, so that aback gate electrode 312 may be formed so as to overlap with the oxidesemiconductor film 304. Since the kind of material, the structure, andthe range of the thickness of the back gate electrode 312 are similar tothose of the back gate electrode 111 described in Embodiment 1,description is omitted here.

When the back gate electrode 312 is formed, an insulating film 313 isformed so as to cover the back gate electrode 312 as illustrated in FIG.9B. Since the kind of material, the structure, and the range of thethickness of the insulating film 313 are similar to those of theinsulating film 112 described in Embodiment 1, description is omittedhere.

A top view of the semiconductor device illustrated in FIG. 9B isillustrated in FIG. 9C. FIG. 9B is a cross-sectional view taken alongdashed line C1-C2 in FIG. 9C.

Note that in this embodiment, an example is described in which thesource electrode and the drain electrode are formed in accordance withthe manufacturing method described in Embodiment 1; however, oneembodiment of the present invention is not limited to this structure.The source electrode and the drain electrode may be formed in accordancewith any of the manufacturing methods described in Embodiments 2 to 4.

This embodiment can be implemented by being combined as appropriate withany of the above-described embodiments.

Embodiment 6

In this embodiment, a method for manufacturing a semiconductor devicewill be described with reference to FIGS. 10A to 10E and FIG. 11 using abottom-contact thin film transistor as an example. Note that the sameportions as Embodiment 1 or portions having functions similar to thoseof Embodiment 1 can be formed as in Embodiment 1, and also the samesteps as Embodiment 1 or the steps similar to those of Embodiment 1 canbe performed in a manner similar to those of Embodiment 1; therefore,repetitive description thereof is omitted.

As illustrated in FIG. 10A, a gate electrode 401 is formed over asubstrate 400 having an insulating surface. An insulating film servingas a base film may be provided between the substrate 400 and the gateelectrode 401. The descriptions of the material, the structure, and thethickness of the gate electrode 101 in Embodiment 1 may be referred tofor the material, the structure, and the thickness of the gate electrode401. The descriptions of the material, the structure, and the thicknessof the base film in Embodiment 1 may be referred to for the material,the structure, and the thickness of the base film.

Next, a gate insulating film 402 is formed over the gate electrode 401.The descriptions of the material, the thickness, the structure, and themanufacturing method of the gate insulating film 102 in Embodiment 1 maybe referred to for the material, the thickness, and the structure, andthe manufacturing method of the gate insulating film 402.

Next, over the gate insulating film 402, a conductive film 405 a formedusing a low electronegativity metal, a low electronegativity metalcompound, or a low electronegativity alloy, and a conductive film 405 bformed using a metal material which has low contact resistance to anoxide semiconductor film 404, such as titanium, tungsten, or molybdenumare sequentially formed. The descriptions of the kind of the material,the structure, and the thickness of the conductive film 105 a and theconductive film 105 b in Embodiment 1 may be referred to for the kind ofthe material, the structure, and the thickness of the conductive film405 b and the conductive film 405 a. In this embodiment, an aluminumfilm having a thickness of 200 nm formed with a sputtering method isused as the conductive film 405 a, and a titanium film having athickness of 100 nm formed with a sputtering method is used as theconductive film 405 b.

After the conductive film 405 a and the conductive film 405 b areformed, the exposed conductive film 405 b may be subjected to heattreatment in a reduced atmosphere or an inert gas atmosphere such as anitrogen atmosphere or a rare gas (argon, helium, or the like)atmosphere. The temperature range of the heat treatment is 200° C. to450° C. as in Embodiment 1. For example, when an aluminum film is usedfor the conductive film 405 a and a titanium film is used for theconductive film 405 b, after wet etching is performed on the conductivefilm 405 b using a solution (ammonia peroxide mixture) containingammonia and oxygenated water, wet etching may be performed on theconductive film 405 a using a solution containing phosphoric acid.Specifically, in this embodiment, an Al-Etchant (an aqueous solutioncontaining nitric acid of 2.0 wt %, acetic acid of 9.8 wt %, andphosphoric acid of 72.3 wt %) produced by Wako Pure Chemical Industries,Ltd. is used as the solution containing phosphoric acid. In addition, asthe ammonia peroxide mixture, specifically, a solution in whichoxygenated water of 31 wt %, ammonia water of 28 wt %, and water aremixed at a volume ratio of 5:2:2 is used. Alternatively, dry etching maybe performed on the conductive film 405 a and the conductive film 405 busing a gas containing chlorine (Cl₂), boron chloride (BCl₃), or thelike.

Next, as illustrated in FIG. 10B, the conductive film 405 a and theconductive film 405 b are processed (patterned) into desired shapes byetching or the like, whereby a source electrode 406 and a drainelectrode 407 are formed.

Next, as illustrated in FIG. 10C, an island-shaped oxide semiconductorfilm 403 is formed over the gate insulating film 402, the sourceelectrode 406, and the drain electrode 407. The descriptions of thematerial, the thickness, the structure, and the manufacturing method ofthe oxide semiconductor film 103 in Embodiment 1 may be referred to forthe material, the thickness, the structure, and the manufacturing methodof the island-shaped oxide semiconductor film 403.

Next, heat treatment is performed on the island-shaped oxidesemiconductor film 403 in a reduced atmosphere, an inert gas atmospheresuch as a nitrogen atmosphere or a rare gas atmosphere, an oxygen gasatmosphere, or an ultra dry air atmosphere (in air whose moisturecontent is less than or equal to 20 ppm (dew point conversion, −55° C.),preferably, less than or equal to 1 ppm, more preferably, less than orequal to 10 ppb in the case where measurement is performed using adew-point meter of a cavity ring-down laser spectroscopy (CRDS) system).The descriptions of the heat treatment performed on the oxidesemiconductor film 103 in Embodiment 1 may be referred to for the heattreatment performed on the oxide semiconductor film 403. The oxidesemiconductor film 403 is subjected to heat treatment in the aboveatmosphere, so that the island-shaped oxide semiconductor film 404 inwhich moisture or hydrogen contained in the oxide semiconductor film 403is eliminated is formed as illustrated in FIG. 10D. Impurities such asmoisture or hydrogen are eliminated by the heat treatment, and theisland-shaped oxide semiconductor film 404 becomes an intrinsic (i-type)semiconductor or a substantially i-type semiconductor; therefore,deterioration of characteristics of the transistor due to theimpurities, such as shifts in threshold voltage, can be prevented frombeing promoted and off-state current can be reduced.

In one embodiment of the present invention, the conductive film 405 a isformed using a low electronegativity metal, a low electronegativitymetal compound, or a low electronegativity alloy, so that impuritiessuch as moisture or hydrogen existing in the oxide semiconductor film404, the gate insulating film 402, or at an interface between the oxidesemiconductor film 404 and another insulating film and the vicinitythereof are occluded or adsorbed by the conductive film 405 a.Therefore, by elimination of impurities such as moisture or hydrogen,the oxide semiconductor film 404 which is an intrinsic (i-type)semiconductor or a substantially i-type semiconductor can be obtained,and deterioration of characteristics of the transistor due to theimpurities, such as shifts in threshold voltage, can be prevented frombeing promoted and off-state current can be reduced.

The conductive film 405 b serving as part of the source electrode 406and the drain electrode 407 is in contact with the oxide semiconductorfilm 404. In addition, since the conductive film 405 b is formed using ametal material having low contact resistance to the oxide semiconductorfilm as described above, contact resistance between the source electrode406 or the drain electrode 407 and the oxide semiconductor film 404 isreduced. Accordingly, on-state current and field-effect mobility of theTFT can be increased.

Then, as illustrated in FIG. 10E, after the source electrode 406 and thedrain electrode 407 are formed, an insulating film 409 is formed so asto cover the oxide semiconductor film 404, the source electrode 406, andthe drain electrode 407. The kind of material, the structure, and therange of the thickness of the insulating film 409 are the same as thoseof the insulating film 109 described in Embodiment 1. In thisembodiment, the insulating film 409 having a structure in which asilicon nitride film having a thickness of 100 nm formed with asputtering method is stacked over a silicon oxide film having athickness of 200 nm formed with a sputtering method is formed. Thesubstrate temperature in film formation may be higher than or equal toroom temperature and lower than or equal to 300° C. and in thisembodiment, is 100° C.

Note that after the insulating film 409 is formed, heat treatment may beperformed. As for the condition of the heat treatment, the condition ofthe heat treatment which is performed after the insulating film 109 isformed in Embodiment 1 may be referred to.

A top view of the semiconductor device illustrated in FIG. 10E isillustrated in FIG. 11. FIG. 10E is a cross-sectional view taken alongdashed line B1-B2 in FIG. 11.

A thin film transistor 410 formed in accordance with the manufacturingmethod has the gate electrode 401; the gate insulating film 402 over thegate electrode 401; the source electrode 406 and the drain electrode 407over the gate insulating film 402; the oxide semiconductor film 404 overthe gate insulating film 402, the source electrode 406, and the drainelectrode 407; and the insulating film 409 over the oxide semiconductorfilm 404, the source electrode 406, and the drain electrode 407.

Next, after a conductive film is formed over the insulating film 409,the conductive film is patterned, so that a back gate electrode may beformed so as to overlap with the oxide semiconductor film 404. Since thekind of material, the structure, and the range of the thickness of theback gate electrode are similar to those of the back gate electrode 111described in Embodiment 1, description is omitted here.

When the back gate electrode is formed, an insulating film is formed soas to cover the back gate electrode. Since the kind of material, thestructure, and the range of the thickness of the insulating film aresimilar to those of the insulating film 112 described in Embodiment 1,description is omitted here.

This embodiment can be implemented by being combined as appropriate withany of the above-described embodiments.

Embodiment 7

In this embodiment, a manufacturing method of a semiconductor displaydevice according to one embodiment of the present invention will bedescribed with reference to FIGS. 12A to 12C, FIGS. 13A and 13B, FIGS.14A and 14B, FIG. 15, FIG. 16, and FIG. 17.

In this specification, in successive film formation, a substrate to beprocessed is placed in an atmosphere which is controlled to be vacuum oran inert gas atmosphere (a nitrogen atmosphere or a rare gas atmosphere)at all times without being exposed to a contaminant atmosphere such asair during a process from a first film formation step using a sputteringmethod to a second film formation step using a sputtering method. By thesuccessive formation, a film can be formed while preventing moisture orthe like from being attached again to the substrate to be processedwhich is cleaned.

Performing the process from the first film formation step to the secondfilm formation step in the same chamber is within the scope of thesuccessive formation in this specification.

In addition, the following is also within the scope of the successiveformation in this specification: in the case of performing the processfrom the first film formation step to the second film formation step inplural chambers, the substrate is transferred after the first filmformation step to another chamber without being exposed to air andsubjected to the second film formation.

Note that between the first film formation step and the second filmformation step, a substrate transfer step, an alignment step, aslow-cooling step, a step of heating or cooling the substrate to atemperature which is necessary for the second film formation step, orthe like may be provided. Such a process is also within the scope of thesuccessive formation in this specification.

A step in which liquid is used, such as a cleaning step, wet etching, orresist formation, may be provided between the first film formation stepand the second film formation step. This case is not within the scope ofthe successive formation in this specification.

In FIG. 12A, as a light-transmitting substrate 800, a glass substratemade by a fusion method or a float method; or a metal substrate such asa stainless steel alloy substrate, provided with an insulating film overits surface may be used. A substrate formed from a flexible syntheticresin, such as plastic, generally tends to have a low upper temperaturelimit, but can be used as the substrate 800 as long as the substrate canwithstand processing temperatures in the later manufacturing process.Examples of a plastic substrate include polyester typified bypolyethylene terephthalate (PET), polyethersulfone (PES), polyethylenenaphthalate (PEN), polycarbonate (PC), polyetheretherketone (PEEK),polysulfone (PSF), polyetherimide (PEI), polyarylate (PAR), polybutyleneterephthalate (PBT), polyimide, acrylonitrile-butadiene-styrene resin,polyvinyl chloride, polypropylene, polyvinyl acetate, acrylic resin, andthe like.

As the glass substrate, the one whose strain point is higher than orequal to 730° C. may be used in the case where the temperature of theheat treatment to be performed later is high. As the glass substrate, aglass material such as aluminosilicate glass, aluminoborosilicate glass,or barium borosilicate glass is used, for example. Note that bycontaining a larger amount of barium oxide (BaO) than boron oxide, aglass substrate is heat-resistant and of more practical use.

Note that as the above glass substrate, a substrate formed using aninsulator such as a ceramic substrate, a quartz substrate, or a sapphiresubstrate may be used. Alternatively, crystallized glass or the like maybe used.

Next, after a conductive film is formed over an entire surface of thesubstrate 800, a first photolithography step is performed to form aresist mask, and unnecessary portions of the conductive film are removedby etching to form wirings and an electrode (a gate wiring including agate electrode 801, a capacitor wiring 822, and a first terminal 821).At this time, etching is performed so that at least end portions of thegate electrode 801 may be tapered.

The conductive film can be formed with a single layer or a stacked layerusing one or more of metal materials such as molybdenum, titanium,chromium, tantalum, tungsten, neodymium, or scandium; an alloy materialwhich includes any of these metal materials as a main component; or anitride of any of these metals. Note that aluminum or copper can be usedas the metal material as long as aluminum or copper can withstandtemperature of heat treatment to be performed in a later process.

For example, as the conductive film having a two-layer structure, thefollowing structures are preferable: a two-layer structure in which amolybdenum layer is stacked over an aluminum layer, a two-layerstructure in which a molybdenum layer is stacked over a copper layer, atwo-layer structure in which a titanium nitride layer or a tantalumnitride layer is stacked over a copper layer, and a two-layer structureof a titanium nitride layer and a molybdenum layer. As a three-layerstructure, the following structure is preferable: a stacked structurecontaining aluminum, an alloy of aluminum and silicon, an alloy ofaluminum and titanium, or an alloy of aluminum and neodymium in a middlelayer and any of tungsten, tungsten nitride, titanium nitride, andtitanium in a top layer and a bottom layer.

In addition, a light-transmitting oxide conductive film is used for partof the electrode and the wiring to increase the aperture ratio. Forexample, indium oxide, an alloy of indium oxide and tin oxide, an alloyof indium oxide and zinc oxide, zinc oxide, aluminum zinc oxide,aluminum zinc oxynitride, gallium zinc oxide, or the like can be used asthe oxide conductive film.

The thickness of each of the gate electrode 801, the capacitor wiring822, and the first terminal 821 is 10 nm to 400 nm, preferably 100 nm to200 nm. In this embodiment, a conductive film for a gate electrode isformed to have a thickness of 100 nm with a sputtering method using atungsten target. Then, the conductive film is processed (patterned) intoa desired shape by etching, whereby the gate electrode 801, thecapacitor wiring 822, and the first terminal 821 are formed.

Note that an insulating film to serve as a base film may be formedbetween the substrate 800 and the gate electrode 801, the capacitorwiring 822, and the first terminal 821. As the base film, for example, asingle layer or a stacked layer using one or more films selected from asilicon oxide film, a silicon oxynitride film, a silicon nitride film, asilicon nitride oxide film, an aluminum nitride film, and an aluminumnitride oxide film can be used. In particular, an insulating film havinga high barrier property, for example, a silicon nitride film, a siliconnitride oxide film, an aluminum nitride film, or an aluminum nitrideoxide film is used for the base film, so that impurities in anatmosphere, such as moisture or hydrogen, or impurities included in thesubstrate 800, such as an alkali metal or a heavy metal, can beprevented from entering the oxide semiconductor film, the gateinsulating film or at the interface between the oxide semiconductor filmand another insulating film and the vicinity thereof.

Next, a gate insulating film 802 is formed over the gate electrode 801,the capacitor wiring 822, and the first terminal 821 as illustrated inFIG. 12B. The gate insulating film 802 can be formed to have a singlelayer of a silicon oxide film, a silicon nitride film, a siliconoxynitride film, a silicon nitride oxide film, an aluminum oxide film,or a tantalum oxide film or a stacked layer thereof with a plasmaenhanced CVD method, a sputtering method, or the like. It is preferablethat the gate insulating film 802 include impurities such as moisture orhydrogen as little as possible. The gate insulating film 802 may have astructure in which an insulating film formed using a material having ahigh barrier property and an insulating film having lower proportion ofnitrogen such as a silicon oxide film or a silicon oxynitride film arestacked. In this case, the insulating film such as a silicon oxide filmor a silicon oxynitride film is formed between the insulating filmhaving a barrier property and the oxide semiconductor film. As theinsulating film having a high barrier property, for example, a siliconnitride film, a silicon nitride oxide film, an aluminum nitride film, analuminum nitride oxide film, or the like can be given. The insulatingfilm having a barrier property is used, so that impurities in anatmosphere, such as moisture or hydrogen, or impurities included in thesubstrate, such as an alkali metal or a heavy metal, can be preventedfrom entering the oxide semiconductor film, the gate insulating film802, or at the interface between the oxide semiconductor film andanother insulating film and the vicinity thereof. In addition, theinsulating film having lower proportion of nitrogen such as a siliconoxide film or a silicon oxynitride film is formed so as to be in contactwith the oxide semiconductor film, so that the insulating film formedusing a material having a high barrier property can be prevented frombeing in contact with the oxide semiconductor film directly.

In this embodiment, the gate insulating film 802 having a structure inwhich a silicon oxide film having a thickness of 100 nm formed with asputtering method is stacked over a silicon nitride film having athickness of 50 nm formed with a sputtering method is formed.

Next, after an oxide semiconductor film is formed over the gateinsulating film 802, the oxide semiconductor film is processed into adesired shape by etching or the like, whereby an island-shaped oxidesemiconductor film 803 is formed. The oxide semiconductor film is formedwith a sputtering method using an oxide semiconductor as a target.Moreover, the oxide semiconductor film can be formed with a sputteringmethod in a rare gas (for example, argon) atmosphere, an oxygenatmosphere, or an atmosphere including a rare gas (for example, argon)and oxygen.

Note that before the oxide semiconductor film is formed with asputtering method, dust attached to a surface of the gate insulatingfilm 802 is preferably removed by reverse sputtering in which an argongas is introduced and plasma is generated. The reverse sputtering refersto a method in which, without application of voltage to a target side,an RF power supply is used for application of voltage to a substrateside in an argon atmosphere and plasma is generated in the vicinity ofthe surface to modify a surface. Note that instead of an argonatmosphere, a nitrogen atmosphere, a helium atmosphere, or the like maybe used. Alternatively, an argon atmosphere to which oxygen, nitrousoxide, or the like is added may be used. Further alternatively, an argonatmosphere to which chlorine, carbon tetrafluoride, or the like is addedmay be used.

For the oxide semiconductor film used for forming a channel formationregion, an oxide material having semiconductor characteristics describedabove may be used.

The thickness of the oxide semiconductor film is set to 10 nm to 300 nm,preferably, 20 nm to 100 nm. Here in this embodiment, the oxidesemiconductor film is formed using an oxide semiconductor target, whichcontains In, Ga, and Zn (the ratio of In₂O₃ to Ga₂O₃ to ZnO is 1:1:1 or1:1:2 in molar ratio) under conditions where the distance between thesubstrate and the target is 100 mm, the pressure is 0.6 Pa, and thedirect current (DC) power is 0.5 kW, and the atmosphere is an oxygenatmosphere (the proportion of the oxygen flow is 100%). Note that apulsed direct current (DC) power supply is preferable because dust canbe reduced and the film thickness can be uniform. In this embodiment, asthe oxide semiconductor film, an In—Ga—Zn—O-based non-single-crystalfilm having a thickness of 30 nm is formed with the use of anIn—Ga—Zn—O-based oxide semiconductor target with a sputtering apparatus.

Note that after the plasma treatment, the oxide semiconductor film isformed without exposure to air, whereby adhesion of dust and moisture toan interface between the gate insulating film 802 and the oxidesemiconductor film can be prevented. Further, a pulsed direct current(DC) power supply is preferable because dust can be reduced and athickness distribution is uniform.

It is preferable that the relative density of the oxide semiconductortarget is greater than or equal to 80%, more preferably, greater than orequal to 95%, further preferably, greater than or equal to 99.9%. When atarget having high relative density is used, the impurity concentrationof the formed oxide semiconductor film can be reduced, and a thin filmtransistor having high electric characteristics or reliability can beobtained.

In addition, there is also a multi-source sputtering apparatus in whicha plurality of targets of different materials can be set. With themulti-source sputtering apparatus, films of different materials can beformed to be stacked in the same chamber, or a film of plural kinds ofmaterials can be formed by electric discharge at the same time in thesame chamber.

In addition, there are a sputtering apparatus provided with a magnetsystem inside the chamber and used for a magnetron sputtering method,and a sputtering apparatus used for an ECR sputtering in which plasmagenerated with the use of microwaves is used without using glowdischarge.

Furthermore, as a film formation method with a sputtering method, thereare also a reactive sputtering method in which a target substance and asputtering gas component are chemically reacted with each other duringfilm formation to form a thin compound film thereof, and a biassputtering method in which voltage is also applied to the substrateduring film formation.

The substrate may be heated at higher than or equal to 400° C. and lowerthan or equal to 700° C. with light or a heater in film formation with asputtering method. The substrate is heated in film formation, wherebythe damage due to sputtering is repaired at the same time as filmformation.

Preheat treatment is preferably performed so as to remove moisture orhydrogen remaining on an inner wall of the sputtering apparatus, on asurface of the target, or in a target material, before the oxidesemiconductor film is formed. As the preheat treatment, a method inwhich the inside of the film deposition chamber is heated to from 200°C. to 600° C. under reduced pressure, a method in which introduction andexhaust of nitrogen or an inert gas are repeated while the inside of afilm deposition chamber is heated, and the like can be given. After thepreheat treatment, the substrate or the sputtering apparatus is cooled,and then the oxide semiconductor film is formed without exposure to air.In this case, not water but oil or the like is preferably used as acoolant for the target. Although a certain level of effect can beobtained when introduction and exhaust of nitrogen are repeated withoutheating, it is more preferable to perform the treatment with the insideof the film formation chamber heated.

It is preferable to remove moisture or the like remaining in thesputtering apparatus with the use of a cryopump before, during, or afterthe oxide semiconductor film is formed.

In a second photolithography step, the oxide semiconductor film isprocessed into a desired shape by wet etching using a solution of amixture of phosphoric acid, acetic acid, and nitric acid for example,whereby the island-shaped oxide semiconductor film 803 can be formed.The island-shaped oxide semiconductor film 803 is formed so as tooverlap with the gate electrode 801. In etching of the oxidesemiconductor film, organic acid such as citric acid or oxalic acid canbe used for an etchant. In this embodiment, the unnecessary portions areremoved by wet etching using ITO07N (product of Kanto Chemical Co.,Inc.), whereby the island-shaped oxide semiconductor film 803 is formed.The etching here is not limited to wet etching and may be dry etching.

As the etching gas for dry etching, a gas containing chlorine(chlorine-based gas such as chlorine (Cl₂), boron chloride (BCl₃),silicon chloride (SiCl₄), or carbon tetrachloride (CCl₄)) is preferablyused.

Alternatively, a gas containing fluorine (fluorine-based gas such ascarbon tetrafluoride (CF₄), sulfur fluoride (SF₆), nitrogen fluoride(NF₃), or trifluoromethane (CHF₃)); hydrogen bromide (HBr); oxygen (O₂);any of these gases to which a rare gas such as helium (He) or argon (Ar)is added; or the like can be used.

As the dry etching method, a parallel plate RIE (reactive ion etching)method or an ICP (inductively coupled plasma) etching method can beused. In order to etch the film into a desired shape, the etchingcondition (the amount of electric power applied to a coil-shapedelectrode, the amount of electric power applied to an electrode on asubstrate side, the temperature of the electrode on the substrate side,or the like) is adjusted as appropriate.

The etchant after the wet etching is removed together with the etchedmaterial by cleaning. The waste liquid including the etchant and theetched material may be purified and the material may be reused. When amaterial such as indium included in the oxide semiconductor film iscollected from the waste liquid after the etching and reused, theresources can be efficiently used and the cost can be reduced.

In order to obtain a desired shape by etching, the etching conditions(such as an etchant, etching time, and temperature) are adjusted asappropriate depending on the material.

Next, as illustrated in FIG. 12C, heat treatment may be performed on theoxide semiconductor film 803 in a reduced atmosphere, an inert gasatmosphere such as a nitrogen atmosphere or a rare gas atmosphere, anoxygen gas atmosphere, or an ultra dry air atmosphere (in air whosemoisture content is less than or equal to 20 ppm (dew point conversion,−55° C.), preferably, less than or equal to 1 ppm, more preferably, lessthan or equal to 10 ppb in the case where measurement is performed usinga dew-point meter of a cavity ring-down laser spectroscopy (CRDS)system). When the heat treatment is performed on the oxide semiconductorfilm 803, an oxide semiconductor film 804 is formed. Specifically, rapidthermal annealing (RTA) treatment can be performed in an inert gasatmosphere (nitrogen, helium, neon, argon, or the like) at a temperatureof higher than or equal to 500° C. and lower than or equal to 750° C.(or lower than or equal to a strain point of a glass substrate) forapproximately greater than or equal to one minute and less than or equalto ten minutes, preferably, at 650° C. for approximately greater than orequal to three minutes and less than or equal to six minutes. With anRTA method, dehydration or dehydrogenation can be performed in a shorttime; therefore, treatment can be performed even at a temperature higherthan the strain point of the glass substrate. Note that the heattreatment is not necessarily performed after the island-shaped oxidesemiconductor film 803 is formed, and the heat treatment may beperformed on the oxide semiconductor film before etching treatment isperformed. The heat treatment may be performed more than once after theisland-shaped oxide semiconductor film 803 is formed.

In this embodiment, heat treatment is performed in a nitrogen atmosphereat 600° C. for six minutes in a state where the substrate temperaturereaches the set temperature. A heating method using an electric furnace,a rapid heating method such as a gas rapid thermal annealing (GRTA)method using a heated gas or a lamp rapid thermal annealing (LRTA)method using lamp light, or the like can be used for the heat treatment.For example, in the case of performing heat treatment using an electricfurnace, the temperature rise characteristics are preferably set athigher than or equal to 0.1° C./min and lower than or equal to 20°C./min and the temperature drop characteristics are preferably set athigher than or equal to 0.1° C./min and lower than or equal to 15°C./min.

Note that it is preferable that in the heat treatment, moisture,hydrogen, or the like be not contained in nitrogen or a rare gas such ashelium, neon, or argon. Alternatively, it is preferable that the purityof nitrogen or the rare gas such as helium, neon, or argon which isintroduced into a heat treatment apparatus be set to be higher than orequal to 6N (99.9999%), preferably higher than or equal to 7N(99.99999%) (that is, the impurity concentration is lower than or equalto 1 ppm, preferably lower than or equal to 0.1 ppm).

Note that a cross-sectional view taken along dashed line D1-D2 and across-sectional view taken along dashed line E1-E2 of FIG. 12Ccorrespond to a cross-sectional view taken along dashed line D1-D2 and across-sectional view taken along dashed line E1-E2 in a top viewillustrated in FIG. 15, respectively.

Next, as illustrated in FIG. 13A, a conductive film 806 used for asource electrode and a drain electrode is formed over the oxidesemiconductor film 804 with a sputtering method or a vacuum evaporationmethod. In this embodiment, the conductive film 806 in which aconductive film 806 b formed using a low electronegativity metal, a lowelectronegativity metal compound, or a low electronegativity alloy isformed over a conductive film 806 a formed using a metal material whichhas low contact resistance to the oxide semiconductor film 804, such astitanium, tungsten, or molybdenum is used.

As the low electronegativity metal, aluminum or magnesium can also beused. A mixture, a metal compound, or an alloy each including one ormore of the above metals can be used for the conductive film 806 b. Whena low heat-resistance material such as aluminum is used, aluminum may becombined with a heat-resistant conductive material such as an elementselected from titanium, tantalum, tungsten, molybdenum, chromium,neodymium, or scandium; an alloy containing one or more of theseelements as its component; or nitride containing the element as itscomponent, so that heat resistance of the conductive film 806 b may beincreased.

The thickness of the conductive film 806 a is preferably 10 nm to 200nm, more preferably, 50 nm to 150 nm. The thickness of the conductivefilm 806 b is preferably 100 nm to 300 nm, more preferably, 150 nm to250 nm. In this embodiment, a titanium film having a thickness of 100 nmformed with a sputtering method is used as the conductive film 806 a,and an aluminum film having a thickness of 200 nm formed with asputtering method is used as the conductive film 806 b.

In one embodiment of the present invention, the conductive film 806 b isformed using a low electronegativity metal, a low electronegativitymetal compound, or a low electronegativity alloy, so that impuritiessuch as moisture or hydrogen existing in the oxide semiconductor film804, the gate insulating film 802, or at an interface between the oxidesemiconductor film 804 and another insulating film and the vicinitythereof are occluded or adsorbed by the conductive film 806 b.Therefore, by elimination of impurities such as moisture or hydrogen,the oxide semiconductor film 804 which is an intrinsic (i-type)semiconductor or a substantially i-type semiconductor can be obtained,and deterioration of characteristics of the transistor due to theimpurities, such as shifts in threshold voltage, can be prevented frombeing promoted and off-state current can be reduced.

In addition to the above structure, the exposed conductive film 806 b issubjected to heat treatment in a reduced atmosphere, or an inert gasatmosphere such as a nitrogen atmosphere or a rare gas (argon, helium,or the like) atmosphere, so that moisture, oxygen, or the like adsorbedon the surface of or inside the conductive film 806 b may be removed.The temperature range of the heat treatment is 200° C. to 450° C. Theheat treatment is performed, so that impurities such as moisture orhydrogen existing in the oxide semiconductor film 804, the gateinsulating film 802 or at the interface between the oxide semiconductorfilm 804 and another insulating film and the vicinity thereof can beeasily occluded or adsorbed by the conductive film 806 b.

Next, as illustrated in FIG. 13B, a third photolithography step isperformed, and the conductive film 806 a and the conductive film 806 bare processed (patterned) into desired shapes by etching or the like,whereby a source electrode 807 and a drain electrode 808 are formed. Forexample, when a titanium film is used for the conductive film 806 a andan aluminum film is used for the conductive film 806 b, after wetetching is performed on the conductive film 806 b using a solutioncontaining phosphoric acid, wet etching may be performed on theconductive film 806 a using a solution (ammonia peroxide mixture)containing ammonia and oxygenated water. Specifically, in thisembodiment, an Al-Etchant (an aqueous solution containing nitric acid of2.0 wt %, acetic acid of 9.8 wt %, and phosphoric acid of 72.3 wt %)produced by Wako Pure Chemical Industries, Ltd. is used as the solutioncontaining phosphoric acid. In addition, as the ammonia peroxidemixture, specifically, a solution in which oxygenated water of 31 wt %,ammonia water of 28 wt %, and water are mixed at a volume ratio of 5:2:2is used. Alternatively, dry etching may be performed on the conductivefilm 806 a and the conductive film 806 b using a gas containing chlorine(Cl₂), boron chloride (BCl₃), or the like.

When the source electrode 807 and the drain electrode 808 are formed bythe patterning, part of an exposed portion of the island-shaped oxidesemiconductor film 804 is etched, so that a groove (a depressed portion)is formed in some cases. In this embodiment, the case in which anisland-shaped oxide semiconductor film 805 having a groove (a depressedportion) is formed by the etching is described. The conductive film 806a serving as part of the source electrode 807 and the drain electrode808 is in contact with the oxide semiconductor film 805. In addition,since the conductive film 806 a is formed using a metal material havinglow contact resistance to the oxide semiconductor film as describedabove, contact resistance between the source electrode 807 or the drainelectrode 808 and the oxide semiconductor film 805 is reduced.Accordingly, on-state current and field-effect mobility of the TFT canbe increased.

In the third photolithography step, a second terminal 820 which isformed from the same material as the source electrode 807 and the drainelectrode 808 is left in a terminal portion. Note that the secondterminal 820 is electrically connected to a source wiring (a sourcewiring including the source electrode 807 and the drain electrode 808).

Further, by use of a resist mask which is formed using a multi-tone maskand has regions with plural thicknesses (for example, two differentthicknesses), the number of resist masks can be reduced, resulting insimplified process and lower costs.

Note that a cross-sectional view taken along dashed line D1-D2 and across-sectional view taken along dashed line E1-E2 of FIG. 13Bcorrespond to a cross-sectional view taken along dashed line D1-D2 and across-sectional view taken along dashed line E1-E2 in a top viewillustrated in FIG. 16, respectively.

Note that in this embodiment, an example is described in which thesource electrode and the drain electrode are formed in accordance withthe manufacturing method described in Embodiment 1; however, the sourceelectrode and the drain electrode may be formed in accordance with anyof the manufacturing methods described in Embodiments 2 to 4.

As illustrated in FIG. 14A, after the source electrode 807 and the drainelectrode 808 are formed, an insulating film 809 is formed so as tocover the source electrode 807, the drain electrode 808, and the oxidesemiconductor film 805. The insulating film 809 preferably includesimpurities such as moisture or hydrogen as little as possible, and theinsulating film 809 may be formed using a single-layer insulating filmor a plurality of insulating films stacked. A material having a highbarrier property is preferably used for the insulating film 809. Forexample, as the insulating film having a high barrier property, asilicon nitride film, a silicon nitride oxide film, an aluminum nitridefilm, an aluminum nitride oxide film, or the like can be used. When aplurality of insulating films stacked is used, an insulating film havinglower proportion of nitrogen than the insulating film having a barrierproperty, such as a silicon oxide film or a silicon oxynitride film, isformed on the side close to the oxide semiconductor film 805. Then, theinsulating film having a barrier property is formed so as to overlapwith the source electrode 807, the drain electrode 808, and the oxidesemiconductor film 805 with the insulating film having lower proportionof nitrogen between the insulating film having a barrier property andthe source electrode 807, the drain electrode 808, and the oxidesemiconductor film 805. When the insulating film having a barrierproperty is used, moisture or oxygen can be prevented from beingadsorbed on the surfaces of or inside the source electrode 807 and thedrain electrode 808. In addition, the impurities such as moisture orhydrogen can be prevented from entering the oxide semiconductor film805, the gate insulating film 802, or at the interface between the oxidesemiconductor film 805 and another insulating film and the vicinitythereof. In addition, the insulating film having lower proportion ofnitrogen such as a silicon oxide film or a silicon oxynitride film isformed so as to be in contact with the oxide semiconductor film 805, sothat the insulating film formed using a material having a high barrierproperty can be prevented from being in contact with the oxidesemiconductor film 805 directly.

In this embodiment, the insulating film 809 having a structure in whicha silicon nitride film having a thickness of 100 nm formed with asputtering method is stacked over a silicon oxide film having athickness of 200 nm formed with a sputtering method is formed. Thesubstrate temperature in film formation may be higher than or equal toroom temperature and lower than or equal to 300° C. and in thisembodiment, is 100° C.

An exposed region of the oxide semiconductor film 805 provided betweenthe source electrode 807 and the drain electrode 808 and the siliconoxide film which forms the insulating film 809 are provided in contactwith each other, so that oxygen is supplied to the region of the oxidesemiconductor film 805 which is in contact with the insulating film 809,and the resistance of the region is increased (carrier concentration isdecreased, preferably, less than 1×10¹⁸/cm³), whereby the oxidesemiconductor film 805 having a channel formation region with highresistance can be formed.

Next, after the insulating film 809 is formed, heat treatment may beperformed. The heat treatment is performed at a temperature of higherthan or equal to 200° C. and lower than or equal to 400° C. (forexample, higher than or equal to 250° C. and lower than or equal to 350°C.) in a reduced atmosphere, an air atmosphere, an inert gas atmosphere(nitrogen, helium, neon, argon, or the like). For example, the secondheat treatment is performed in a nitrogen atmosphere at 250° C. for onehour. Alternatively, RTA treatment may be performed at high temperaturefor a short time as in the previous heat treatment. By the heattreatment, the oxide semiconductor film 805 is heated while being incontact with silicon oxide which forms the insulating film 809. Inaddition, the resistance of the oxide semiconductor film 805 isincreased. Accordingly, electric characteristics of the transistor canbe improved and variation in the electric characteristics thereof can bereduced. There is no particular limitation on when to perform this heattreatment as long as it is performed after the formation of theinsulating film 809. When this heat treatment also serves as heattreatment in another step, for example, heat treatment in formation of aresin film or heat treatment for reducing resistance of a transparentconductive film, the number of steps can be prevented from increasing.

Through the above steps, a thin film transistor 813 can be manufactured.

Next, a fourth photolithography step is performed in such a manner thata resist mask is formed and the insulating film 809 and the gateinsulating film 802 are etched, so that a contact hole is formed toexpose parts of the drain electrode 808, the first terminal 821, and thesecond terminal 820. Next, the resist mask is removed, and then atransparent conductive film is formed. The transparent conductive filmis formed of indium oxide (In₂O₃), an indium oxide-tin oxide alloy(In₂O₃—SnO₂, abbreviated to ITO), or the like with a sputtering method,a vacuum evaporation method, or the like. Such a material is etched witha hydrochloric acid-based solution. However, since a residue is easilygenerated particularly in etching ITO, an indium oxide-zinc oxide alloy(In₂O₃—ZnO) may be used to improve etching processability. Moreover, inthe case where heat treatment for reducing resistance of the transparentconductive film, the heat treatment can also serve as the heat treatmentwhich increases the resistance of the oxide semiconductor film 805 sothat improvement and less variation in electric characteristics of thetransistor may be achieved.

Next, a fifth photolithography step is performed in such a manner that aresist mask is formed and unnecessary portions are removed by etching,so that a pixel electrode 814 which is connected to the drain electrode808, a transparent conductive film 815 which is connected to the firstterminal 821, and a transparent conductive film 816 which is connectedto the second terminal 820 are formed.

The transparent conductive films 815 and 816 function as electrodes orwirings connected to an FPC. The transparent conductive film 815 formedover the first terminal 821 is a connection terminal electrode whichfunctions as an input terminal of the gate wiring. The transparentconductive film 816 formed over the second terminal 820 is a connectionterminal electrode which functions as an input terminal of the sourcewiring.

In this sixth photolithography step, the capacitor wiring 822 and thepixel electrode 814 together form a storage capacitor 819 with the useof the gate insulating film 802 and the insulating film 809 asdielectrics.

A cross-sectional view after the resist mask is removed is illustratedin FIG. 14B. Note that a cross-sectional view taken along dashed lineD1-D2 and a cross-sectional view taken along dashed line E1-E2 of FIG.14B correspond to a cross-sectional view taken along dashed line D1-D2and a cross-sectional view taken along dashed line E1-E2 in a top viewillustrated in FIG. 17, respectively.

Through these six photolithography steps, the storage capacitor 819 anda pixel thin film transistor portion including the thin film transistor813 which is a bottom-gate thin film transistor having an invertedstaggered structure can be completed using the six photomasks. Bydisposing the thin film transistor and the storage capacitor in eachpixel of a pixel portion in which pixels are arranged in a matrix form,one of substrates for manufacturing an active matrix display device canbe obtained. In this specification, such a substrate is referred to asan active matrix substrate for convenience.

In the case of manufacturing an active matrix liquid crystal displaydevice, an active matrix substrate and a counter substrate provided witha counter electrode are bonded to each other with a liquid crystal layerinterposed therebetween.

Alternatively, a storage capacitor may be formed with a pixel electrodewhich overlaps with a gate wiring of an adjacent pixel, with aninsulating film and a gate insulating film interposed therebetween,without provision of the capacitor wiring.

In an active matrix liquid crystal display device, pixel electrodesarranged in a matrix form are driven to form a display pattern on ascreen. Specifically, voltage is applied between a selected pixelelectrode and a counter electrode corresponding to the pixel electrode,so that a liquid crystal layer provided between the pixel electrode andthe counter electrode is optically modulated and this optical modulationis recognized as a display pattern by an observer.

In the case of manufacturing a light-emitting display device, a bankincluding an organic resin film is provided between organiclight-emitting elements in some cases. In that case, heat treatmentperformed on the organic resin film can also serve as the heat treatmentwhich increases the resistance of the oxide semiconductor film 805 sothat improvement and less variation in electric characteristics of thetransistor may be achieved.

The use of an oxide semiconductor for a thin film transistor leads toreduction in manufacturing cost. In particular, impurities such asmoisture, hydrogen, or OH are reduced by heat treatment and the purityof the oxide semiconductor film is increased. Therefore, a semiconductordisplay device including a highly reliable thin film transistor havingfavorable electric characteristics can be manufactured without using anultrapure oxide semiconductor target or a special sputtering apparatusin which dew point in the film deposition chamber is reduced.

Since the semiconductor film in the channel formation region is a regionwhose resistance is increased, electric characteristics of the thin filmtransistor are stabilized, and increase in off current or the like canbe prevented. Therefore, a semiconductor display device including highlyreliable thin film transistors having favorable electric characteristicscan be provided.

This embodiment can be implemented in combination with embodiments abovementioned.

Embodiment 8

In this embodiment, a structure of a semiconductor display device whichis referred to as electronic paper or digital paper and which is one ofthe semiconductor display devices formed using a manufacturing method ofthe present invention will be described.

A display element which can control grayscale by voltage application andhas memory characteristics is used for electronic paper. Specifically,in the display element used for the electronic paper, a display elementsuch as a non-aqueous electrophoretic display element; a display elementwhich uses a PDLC (polymer dispersed liquid crystal) method, in whichliquid crystal droplets are dispersed in a high polymer material whichis between two electrodes; a display element which includes chiralnematic liquid crystal or cholesteric liquid crystal between twoelectrodes; a display element which includes charged fine particlesbetween two electrodes and employs a particle-moving method in which thecharged fine particles are moved through fine particles by using anelectric field; or the like can be used. Further, a non-aqueouselectrophoretic display element may be a display element in which adispersion liquid, in which charged fine particles are dispersed, issandwiched between two electrodes; a display element in which adispersion liquid in which charged fine particles are dispersed isincluded over two electrodes between which an insulating film isinterposed; a display element in which twisting balls having hemisphereswhich are different colors which charge differently are dispersed in asolvent between two electrodes; a display element which includesmicrocapsules, in which a plurality of charged fine particles isdispersed in a solution, between two electrodes; or the like.

A top view of a pixel portion 700, a signal line driver circuit 701, anda scan line driver circuit 702 of electronic paper is illustrated inFIG. 18A.

The pixel portion 700 includes a plurality of pixels 703. A plurality ofsignal lines 707 extended from the signal line driver circuit 701 is ledin the pixel portion 700. A plurality of scan lines 708 from the scanline driver circuit 702 is led in the pixel portion 700.

Each pixel 703 includes a transistor 704, a display element 705, and astorage capacitor 706. A gate electrode of the transistor 704 isconnected to one of the scan lines 708. One of a source electrode and adrain electrode of the transistor 704 is connected to one of the signallines 707, and the other of the source electrode and the drain electrodeof the transistor 704 is connected to a pixel electrode of the displayelement 705.

Note that in FIG. 18A, the storage capacitor 706 is connected inparallel to the display element 705 so that voltage applied between thepixel electrode and a counter electrode of the display element 705 maybe stored; however, in the case where the memory property of the displayelement 705 is sufficiently high that display can be maintained, thestorage capacitor 706 is not necessarily provided.

Although an active matrix pixel portion structure in which onetransistor which serves as a switching element is provided in each pixelis illustrated in FIG. 18A, the electronic paper of one embodiment ofthe present invention is not limited to this structure. A plurality oftransistors may be provided in each pixel. Further, besides transistors,elements such as capacitors, resistors, coils, or the like may also beconnected to the pixels.

A cross-sectional view of the display element 705 provided in each pixel703 is illustrated in FIG. 18B taking an electrophoretic electronicpaper having microcapsules as an example.

The display element 705 has a pixel electrode 710, a counter electrode711, and a microcapsule 712 to which voltage is applied by the pixelelectrode 710 and the counter electrode 711. One of a source electrodeand a drain electrode 713 of the transistor 704 is connected to thepixel electrode 710.

In the microcapsule 712, positively charged white pigment such astitanium oxide and negatively charged black pigment such as carbon blackare encapsulated together with a dispersion medium such as oil. Inaccordance with the voltage of a video signal applied to the pixelelectrode 710, voltage is applied between the pixel electrode and thecounter electrode, and the negatively charged black pigment is attractedto a positive electrode side and the positively charged white pigment isattracted to a negative electrode side, whereby gray scales can bedisplayed.

In FIG. 18B, the microcapsule 712 is fixed between the pixel electrode710 and the counter electrode 711 using a light-transmitting resin 714.However, one embodiment of the present invention is not limited to thisstructure, and a space formed by the microcapsule 712, the pixelelectrode 710, and the counter electrode 711 may be filled with a gassuch as air, an inert gas, or the like. Note that in this case, themicrocapsule 712 is preferably fixed to one of or both the pixelelectrode 710 and the counter electrode 711 using an adhesive agent orthe like.

The number of the microcapsules 712 included in the display element 705is not always more than one as illustrated in FIG. 18B. One displayelement 705 may have a plurality of the microcapsules 712, or aplurality of the display elements 705 may have one microcapsule 712. Forexample, when two display elements 705 share one microcapsule 712,positive voltage is applied to the pixel electrode 710 included in oneof the display elements 705 and negative voltage is applied to the pixelelectrode 710 included in the other display element 705. In this case,in a region of the microcapsule 712 which overlaps with the pixelelectrode 710 to which positive voltage is applied, the black pigment isattracted to the pixel electrode 710 side and the white pigment isattracted to the counter electrode 711 side. On the other hand, in aregion of the microcapsule 712 which overlaps with the pixel electrode710 to which negative voltage is applied, the white pigment is attractedto the pixel electrode 710 side and the black pigment is attracted tothe counter electrode 711 side.

Next, a specific driving method of the electronic paper will bedescribed taking the electrophoretic electronic paper as an example.

The operation of the electronic paper can be described using threeperiods: an initialization period, a write period, and a retentionperiod.

Before a displayed image is switched, first, a display element isinitialized by unifying gray scale levels of each pixel in a pixelportion in the initialization period.

The display element is initialized, whereby an afterimage can beprevented from remaining. Specifically, in the electrophoreticelectronic paper, a gray scale displayed by the microcapsule 712included in the display element 705 is adjusted so that each pixel maydisplay white or black.

In this embodiment, the operation of initialization in which after avideo signal for initialization such that black is displayed is input tothe pixel, a video signal for initialization such that white isdisplayed is input to the pixel will be described. For example, in thecase of electrophoretic electronic paper in which display of an image isperformed towards the counter electrode 711 side, first, voltage isapplied to the display element 705 so that the black pigment may beattracted to the counter electrode 711 side and the white pigment may beattracted to the pixel electrode 710 side in the microcapsule 712. Next,voltage is applied to the display element 705 so that the white pigmentis attracted to the counter electrode 711 side and the black pigment isattracted to the pixel electrode 710 side in the microcapsule 712.

If a video signal for initialization is input to the pixel only once,depending on a gray scale which has been displayed before theinitialization period, transfer of the white pigment and the blackpigment in the microcapsule 712 ends in mid-stream, and there might be adifference in a gray scale to be displayed among the pixels when theinitialization period is terminated. Therefore, it is preferable thatvoltage −Vp which is negative with respect to common voltage Vcom beapplied to the pixel electrode 710 more than once, so that black may bedisplayed, whereas voltage Vp which is positive with respect to thecommon voltage Vcom be applied to the pixel electrode 710 more thanonce, so that white may be displayed.

Note that when gray scales displayed by display elements of each pixeldiffer before the initialization period, the minimum number of times ofinputting video signals for initialization varies. Accordingly, thenumber of times of inputting video signals for initialization may bechanged among the pixels in accordance with the gray scales which havebeen displayed before the initialization period. In this case, thecommon voltage Vcom may be input to the pixel which does not need toinput a video signal for initialization.

Note that in order to apply voltage Vp or voltage −Vp of the videosignal for initialization to the pixel electrode 710 more than once, ina period where a pulse of a selection signal is provided to each scanline, a series of operations are performed more than once in which thevideo signal for initialization is input to the pixels in a line havingthe scan line. When voltage Vp or voltage −Vp of the video signal forinitialization is applied to the pixel electrode 710 more than once,transfer of the white pigment and the black pigment in the microcapsule712 converges and a difference in a gray scale level among the pixels isprevented, whereby the pixel in the pixel portion can be initialized.

Note that in the initialization period, black may be displayed afterwhite is displayed instead of displaying white after black is displayedin each pixel. Alternatively, in the initialization period, black may bedisplayed after white is displayed in each pixel, and then white may bedisplayed.

Further, as for all of the pixels in the pixel portion, the timing ofstarting the initialization period is not necessarily the same. Forexample, the timing of starting the initialization period may bedifferent among every pixel, or every pixel belonging to the same line,or the like.

Next, in the write period, a video signal having image information isinput to the pixel.

When an image is displayed on the whole pixel portion, the selectionsignal in which pulses of voltage sequentially shift through all thescan lines is input in one frame period. Then, in one line period whenthe pulse appears in the selection signal, a video signal having imageinformation is input to all the signal lines.

In accordance with the voltage of a video signal applied to the pixelelectrode 710, the white pigment and the black pigment in themicrocapsule 712 transfer to the pixel electrode 710 side or the counterelectrode 711 side, so that the display element 705 displays a grayscale.

Note that also in the write period, it is preferable that the voltage ofa video signal be applied to the pixel electrode 710 more than once in amanner similar to that in the initialization period. Accordingly, in theperiod when a pulse of a selection signal is supplied to each scan line,a series of operations are performed more than once in which a videosignal is input to the pixels in a line having the scan line.

Next, in the retention period, after the common voltage Vcom is input toall the pixels through the signal line, a selection signal is not inputto the scan line or a video signal is not input to the signal line.Accordingly, since the arrangement of the white pigment and the blackpigment in the microcapsule 712 included in the display element 705 iskept at the same position unless positive or negative voltage is appliedbetween the pixel electrode 710 and the counter electrode 711, a grayscale which is displayed by the display element 705 is kept. Therefore,an image written in the write period is held also in the retentionperiod.

Note that voltage required to change the gray scale levels of thedisplay element used for electronic paper tends to be higher than thoseof a liquid crystal element used for a liquid crystal display device ora light-emitting element such as an organic light-emitting element usedfor a light-emitting device. Therefore, in the write period, a potentialdifference between a source electrode and a drain electrode of thetransistor 704 used as a switching element in the pixel increases, sothat the off-state current of the transistor 704 increases; therefore apotential of the pixel electrode 710 fluctuates and distorted imageseasily occur. It is effective to increase the capacity of the storagecapacitor 706 in order to prevent the potential of the pixel electrode710 from fluctuating due to the off-state current of the transistor 704.In addition, not only voltage generated between the pixel electrode 710and the counter electrode 711 but also voltage generated between thesignal line 707 and the counter electrode 711 is applied to themicrocapsule 712, so that distorted images are displayed by the displayelement 705 in some cases. In order to prevent generation of thisdistorted image, it is effective to have a large area of the pixelelectrode 710 and to prevent application of voltage which is generatedbetween the signal line 707 and the counter electrode 711 to themicrocapsule 712. However, as described above, when the capacity of thestorage capacitor 706 increases in order to prevent fluctuation of thepotential of the pixel electrode 710 or the area of the pixel electrode710 increases in order to prevent generation of distorted images on thedisplay, a current value which should be supplied to the pixel in thewrite period increases, so that it takes time to input a video signal.In the electronic paper of one embodiment of the present invention, thetransistor 704 used as a switching element in the pixel has high fieldeffect mobility, so that high on-state current can be obtained.Accordingly, even when the capacity of the storage capacitor 706increases or even when the area of the pixel electrode 710 increases, avideo signal can be input to the pixel quickly. Therefore, the length ofthe write period can be suppressed, and displayed images can be switchedsmoothly. In addition, the potential difference between the sourceelectrode and the drain electrode of the transistor 704 used as aswitching element in the pixel increases in the write period, so thatthe transistor 704 easily deteriorates. However, in one embodiment ofthe present invention, variation in threshold voltage of the transistor704 due to degradation over time can be reduced, so that reliability ofthe electronic paper can be enhanced.

This embodiment can be implemented in combination with embodiments abovementioned.

Embodiment 9

FIG. 19A is an example of a block diagram of an active matrixsemiconductor display device. Over a substrate 5300 in the displaydevice, a pixel portion 5301, a first scan line driver circuit 5302, asecond scan line driver circuit 5303, and a signal line driver circuit5304 are provided. In the pixel portion 5301, a plurality of signallines which is extended from the signal line driver circuit 5304 isprovided and a plurality of scan lines which is extended from the firstscan line driver circuit 5302 and the second scan line driver circuit5303 is provided. Note that pixels which include display elements areprovided in a matrix form in respective regions where the scan lines andthe signal lines intersect with each other. Further, the substrate 5300in the display device is connected to a timing control circuit 5305(also referred to as a controller or a controller IC) through aconnection point such as a flexible printed circuit (FPC).

In FIG. 19A, the first scan line driver circuit 5302, the second scanline driver circuit 5303, and the signal line driver circuit 5304 areformed over one substrate 5300 where the pixel portion 5301 is formed.Therefore, a decrease in the number of parts provided outside, such as adriver circuit, enables not only downsizing of a display device but alsoreduction in cost due to the decrease in the number of assembly stepsand inspection steps. In addition, in the case where a driver circuit isprovided outside the substrate 5300, wirings would need to be extendedand the number of the connections of wirings would be increased, but byproviding the driver circuit over the substrate 5300, the number ofconnections of the wirings can be reduced. Accordingly, the decrease inyield due to poor connection between the driver circuit and the pixelportion can be prevented, and the decrease in reliability due to lowmechanical strength of a connection point can be prevented.

Note that for example, the timing control circuit 5305 supplies a firstscan line driver circuit start signal (GSP1) (a start signal is alsoreferred to as a start pulse) and a scan line driver circuit clocksignal (GCK1) to the first scan line driver circuit 5302. The timingcontrol circuit 5305 supplies, for example, a second scan line drivercircuit start signal (GSP2) and a scan line driver circuit clock signal(GCK2) to the second scan line driver circuit 5303. Moreover, the timingcontrol circuit 5305 supplies a signal line driver circuit start signal(SSP), a signal line driver circuit clock signal (SCK), video signaldata (DATA, also simply referred to as a video signal), and a latchsignal (LAT) to the signal line driver circuit 5304. One of the firstscan line driver circuit 5302 and the second scan line driver circuit5303 can be omitted.

FIG. 19B illustrates a structure in which circuits with low drivingfrequency (for example, the first scan line driver circuit 5302 and thesecond scan line driver circuit 5303) are formed over one substrate 5300where the pixel portion 5301 is formed and the signal line drivercircuit 5304 is formed over a different substrate from the pixel portion5301. In the signal line driver circuit 5304, a circuit with low drivingfrequency such as an analog switch used for a sampling circuit can bepartly formed over one substrate 5300 where the pixel portion 5301 isformed. In this manner, a system on panel is partly adopted, so thatadvantages of the system on panel can be given to some extent; forexample, a decrease in yield due to the above-described poor connection,a decrease in the mechanical strength of a connection portion, and thelike are prevented, and cost is reduced because of the decrease in thenumber of assembly steps and inspection steps. Further, performance of acircuit with high driving frequency can be enhanced by comparison withthe case where all of the pixel portion 5301, the scan line drivercircuit 5302, the scan line driver circuit 5303, and the signal linedriver circuit 5304 are formed over one substrate as a system-on-panel,and a pixel portion with a wide area, which is difficult to be realizedin the case of using a single crystal semiconductor, can be formed.

Next, a structure of a signal line driver circuit formed using ann-channel transistor will be described.

The signal line driver circuit illustrated in FIG. 20A includes a shiftregister 5601 and a sampling circuit 5602. The sampling circuit 5602includes a plurality of switching circuits 5602_1 to 5602_N (N is anatural number). The switching circuits 5602_1 to 5602_N are eachconstituted by a plurality of n-channel transistors 5603_1 to 5603_k (kis a natural number).

A connection relation of the signal line driver circuit will bedescribed using the switching circuit 5602_1 as an example. Note thatone of a source electrode and a drain electrode of a transistor isdenoted as a first terminal, and the other is denoted to as a secondterminal below.

First terminals of the transistors 5603_1 to 5603_k are connected towirings 5604_1 to 5604_k, respectively. Note that a video signal isinput to each of the wirings 5604_1 to 5604_k. Second terminals of thetransistors 5603_1 to 5603_k are connected to signal lines S1 to Sk,respectively. Gate electrodes of the transistors 5603_1 to 5603_k areconnected to the shift register 5601.

The shift register 5601 has a function of sequentially selecting theswitching circuits 5602_1 to 5602_N by sequentially outputting a timingsignal having high level (H-level) voltage to wirings 5605_1 to 5605_N.

The switching circuit 5602_1 has a function of controlling electricalcontinuity between the wirings 5604_1 to 5604_k and the signal lines S1to Sk (conduction between the first terminal and the second terminal)due to the switching of the transistors 5603_1 to 5603_k, namely afunction of controlling whether or not to supply potentials of thewirings 5604_1 to 5604_k to the signal lines S1 to Sk.

Next, the operation of the signal line driver circuit in FIG. 20A isdescribed with reference to a timing chart in FIG. 20B. In FIG. 20B, thetiming chart of the timing signals Sout_1 to Sout_N which are input fromthe shift register 5601 to the wirings 5605_1 to 5605_N and videosignals Vdata_1 to Vdata_k which are input to the wirings 5604_1 to5604_k is illustrated as an example.

Note that one operation period of the signal line driver circuitcorresponds to one line period in a display device. In FIG. 20B, thecase is illustrated in which one line period is divided into periods T1to TN. Each of the periods T1 to TN is a period for writing the videosignal into one pixel in a selected line.

In the periods T1 to TN, the shift register 5601 sequentially outputsH-level timing signals to the wirings 5605_1 to 5605_N. For example, inthe period T1, the shift register 5601 outputs an H level signal to thewiring 5605_1. Then, the transistors 5603_1 to 5603_k included in theswitching circuit 5602_1 are turned on, so that the wirings 5604_1 to5604_k and the signal lines S1 to Sk are brought into conduction. Inthis case, Data (S1) to Data (Sk) are input to the wirings 5604_1 to5604_k, respectively. The Data (S1) to Data (Sk) are input to pixels inthe first to kth columns in the selected row through the transistors5603_1 to 5603_k. Thus, in the periods T1 to TN, video signals aresequentially written to the pixels in the selected row by k columns.

By writing video signals to pixels by a plurality of columns, the numberof video signals or the number of wirings can be reduced. Thus, thenumber of connections to an external circuit such as a controller can bereduced. By writing video signals to pixels of every plurality ofcolumns, write time can be extended and insufficient writing of videosignals can be prevented.

Next, one embodiment of a shift register which is used for a signal linedriver circuit or a scan line driver circuit is described with referenceto FIGS. 21A and 21B and FIGS. 22A and 22B.

The shift register includes first to Nth pulse output circuits 10_1 to10_N (N is a natural number of 3 or more) (see FIG. 21A). A first clocksignal CK1, a second clock signal CK2, a third clock signal CK3, and afourth clock signal CK4 are supplied from a first wiring 11, a secondwiring 12, a third wiring 13, and a fourth wiring 14, respectively, tothe first to Nth pulse output circuits 10_1 to 10_N. A start pulse SP1(a first start pulse) from a fifth wiring 15 is input to the first pulseoutput circuit 10_1. Further, a signal from the pulse output circuit10_(n−1) of the previous stage (referred to as a previous stage signalOUT (n−1)) is input to the nth pulse output circuit 10_n (n is a naturalnumber of 2 or more and N or less) in a second or subsequent stage. Asignal from the third pulse output circuit 10_3 which is two stagesafter the first pulse output circuit 10_1 is input to the first pulseoutput circuit 10_1. In a similar way, a signal from the (n+2)th pulseoutput circuit 10_(n+2) which is two stages after the nth pulse outputcircuit 10_n (referred to as the subsequent stage signal OUT(n+2)) isinput to the nth pulse output circuit 10_n in the second stage orsubsequent stage. Thus, the pulse output circuits of the respectivestages output first output signals (OUT(1)(SR) to OUT(N)(SR)) to beinput to the pulse output circuit of the subsequent stage and/or to thepulse output circuit of the stage before the previous stage, and secondoutput signals (OUT(1) to OUT(N)) to be input to another circuit or thelike. Note that as illustrated in FIG. 21A, a subsequent stage signalOUT(n+2) is not input to the last two stages of the shift register;therefore, as an example, a second start pulse SP2 and a third startpulse SP3 may be input thereto, respectively.

Note that the clock signal (CK) is a signal which alternates between anH level and an L level (low level voltage) at a regular interval. Thefirst to fourth clock signals (CK1) to (CK4) are delayed by ¼ periodsequentially. In this embodiment, by using the first to fourth clocksignals (CK1) to (CK4), control or the like of driving of a pulse outputcircuit is performed. Note that the clock signal is also called GCK orSCK in accordance with a driver circuit to which the clock signal isinput; however, description is made using CK as the clock signal.

A first input terminal 21, a second input terminal 22, and a third inputterminal 23 are electrically connected to any of the first to fourthwirings 11 to 14. For example, in FIG. 21A, the first input terminal 21of the first pulse output circuit 10_1 is electrically connected to thefirst wiring 11, the second input terminal 22 of the first pulse outputcircuit 10_1 is electrically connected to the second wiring 12, and thethird input terminal 23 of the first pulse output circuit 10_1 iselectrically connected to the third wiring 13. In addition, the firstinput terminal 21 of the second pulse output circuit 10_2 iselectrically connected to the second wiring 12, the second inputterminal 22 of the second pulse output circuit 10_2 is electricallyconnected to the third wiring 13, and the third input terminal 23 of thesecond pulse output circuit 10_2 is electrically connected to the fourthwiring 14.

Each of the first to Nth pulse output circuits 10_1 to 10_N includes thefirst input terminal 21, the second input terminal 22, the third inputterminal 23, a fourth input terminal 24, a fifth input terminal 25, afirst output terminal 26, and a second output terminal 27 (see FIG.21B). In the first pulse output circuit 10_1, the first clock signal CK1is input to the first input terminal 21; the second clock signal CK2 isinput to the second input terminal 22; the third clock signal CK3 isinput to the third input terminal 23; the start pulse is input to thefourth input terminal 24; the subsequent stage signal OUT(3) is input tothe fifth input terminal 25; the first output signal OUT(1)(SR) isoutput from the first output terminal 26; and the second output signalOUT (1) is output from the second output terminal 27.

Next, an example of a specific circuit structure of a pulse outputcircuit will be described with reference to FIG. 22A.

Each pulse output circuit includes first to thirteenth transistors 31 to43 (see FIG. 22A). Signals or power supply potentials are supplied tothe first to thirteenth transistors 31 to 43 from a power supply line 51which supplies a first high power supply potential VDD, a power supplyline 52 which supplies a second high power supply potential VCC, and apower supply line 53 which supplies a low power supply potential VSS, inaddition to the above-described first to fifth input terminals 21 to 25,the first output terminal 26, and the second output terminal 27. Therelation of the power supply potentials of the power supply lines inFIG. 22A is as follows: the first power supply potential VDD is higherthan or equal to the second power supply potential VCC, and the secondpower supply potential VCC is higher than the third power supplypotential VSS. The first to fourth clock signals (CK1) to (CK4) aresignals which become H-level signals and L-level signals repeatedly at aregular interval. The potential is VDD when the clock signal is at the Hlevel, and the potential is VSS when the clock signal is at the L level.By making the first power supply potential VDD of the power supply line51 higher than the second power supply potential VCC of the power supplyline 52, a potential applied to a gate electrode of a transistor can belowered, shift in threshold voltage of the transistor can be reduced,and deterioration of the transistor can be suppressed without an adverseeffect on the operation of the transistor.

In FIG. 22A, a first terminal of the first transistor 31 is electricallyconnected to the power supply line 51, a second terminal of the firsttransistor 31 is electrically connected to a first terminal of the ninthtransistor 39, and a gate electrode of the first transistor 31 iselectrically connected to the fourth input terminal 24. A first terminalof the second transistor 32 is electrically connected to the powersupply line 53, a second terminal of the second transistor 32 iselectrically connected to the first terminal of the ninth transistor 39,and a gate electrode of the second transistor 32 is electricallyconnected to a gate electrode of the fourth transistor 34. A firstterminal of the third transistor 33 is electrically connected to thefirst input terminal 21, and a second terminal of the third transistor33 is electrically connected to the first output terminal 26. A firstterminal of the fourth transistor 34 is electrically connected to thepower supply line 53, and a second terminal of the fourth transistor 34is electrically connected to the first output terminal 26. A firstterminal of the fifth transistor 35 is electrically connected to thepower supply line 53, a second terminal of the fifth transistor 35 iselectrically connected to the gate electrode of the second transistor 32and the gate electrode of the fourth transistor 34, and a gate electrodeof the fifth transistor 35 is electrically connected to the fourth inputterminal 24. A first terminal of the sixth transistor 36 is electricallyconnected to the power supply line 52, a second terminal of the sixthtransistor 36 is electrically connected to the gate electrode of thesecond transistor 32 and the gate electrode of the fourth transistor 34,and a gate electrode of the sixth transistor 36 is electricallyconnected to the fifth input terminal 25. A first terminal of theseventh transistor 37 is electrically connected to the power supply line52, a second terminal of the seventh transistor 37 is electricallyconnected to a second terminal of the eighth transistor 38, and a gateelectrode of the seventh transistor 37 is electrically connected to thethird input terminal 23. A first terminal of the eighth transistor 38 iselectrically connected to the gate electrode of the second transistor 32and the gate electrode of the fourth transistor 34, and a gate electrodeof the eighth transistor 38 is electrically connected to the secondinput terminal 22. The first terminal of the ninth transistor 39 iselectrically connected to the second terminal of the first transistor 31and the second terminal of the second transistor 32, a second terminalof the ninth transistor 39 is electrically connected to a gate electrodeof the third transistor 33 and a gate electrode of the tenth transistor40, and a gate electrode of the ninth transistor 39 is electricallyconnected to the power supply line 52. A first terminal of the tenthtransistor 40 is electrically connected to the first input terminal 21,a second terminal of the tenth transistor 40 is electrically connectedto the second output terminal 27, and the gate electrode of the tenthtransistor 40 is electrically connected to the second terminal of theninth transistor 39. A first terminal of the eleventh transistor 41 iselectrically connected to the power supply line 53, a second terminal ofthe eleventh transistor 41 is electrically connected to the secondoutput terminal 27, and a gate electrode of the eleventh transistor 41is electrically connected to the gate electrode of the second transistor32 and the gate electrode of the fourth transistor 34. A first terminalof the twelfth transistor 42 is electrically connected to the powersupply line 53, a second terminal of the twelfth transistor 42 iselectrically connected to the second output terminal 27, and a gateelectrode of the twelfth transistor 42 is electrically connected to thegate electrode of the seventh transistor 37. A first terminal of thethirteenth transistor 43 is electrically connected to the power supplyline 53, a second terminal of the thirteenth transistor 43 iselectrically connected to the first output terminal 26, and a gateelectrode of the thirteenth transistor 43 is electrically connected tothe gate electrode of the seventh transistor 37.

In FIG. 22A, a connection point of the gate electrode of the thirdtransistor 33, the gate electrode of the tenth transistor 40, and thesecond terminal of the ninth transistor 39 is referred to as a node A. Aconnection point where the gate electrode of the second transistor 32,the gate electrode of the fourth transistor 34, the second terminal ofthe fifth transistor 35, the second terminal of the sixth transistor 36,the first terminal of the eighth transistor 38, and the gate electrodeof the eleventh transistor 41 are connected is referred to as a node B(see FIG. 22A).

FIG. 22B illustrates a timing chart of a shift register including aplurality of the pulse output circuits illustrated in FIG. 22A.

Note that as illustrated in FIG. 22A, by providing of the ninthtransistor 39 whose gate electrode is supplied with the second powersupply potential VCC, advantages described below are obtained before andafter bootstrap operation.

Without the ninth transistor 39 in which the second power supplypotential VCC is applied to the gate electrode, if a potential of thenode A is raised by the bootstrap operation, a potential of the sourceelectrode which is the second terminal of the first transistor 31 risesto a value higher than the first power supply potential VDD. Then, thefirst terminal of the first transistor 31, namely the power supply line51, becomes to serve as the source electrode thereof. Consequently, inthe first transistor 31, high bias voltage is applied and thussignificant stress is applied between the gate electrode and the sourceelectrode and between the gate electrode and the drain electrode, whichmight cause deterioration of the transistor. By providing of the ninthtransistor 39 whose gate electrode is supplied with the second powersupply potential VCC, the potential of the node A is raised by thebootstrap operation, but at the same time, an increase in the potentialof the second terminal of the first transistor 31 can be prevented. Inother words, the placement of the ninth transistor 39 can lower thelevel of negative bias voltage applied between the gate electrode andthe source electrode of the first transistor 31. Accordingly, with acircuit structure in this embodiment, negative bias voltage appliedbetween the gate electrode and the source electrode of the firsttransistor 31 can be lowered, so that deterioration of the firsttransistor 31, which is due to stress, can be further restrained.

Note that the ninth transistor 39 is provided so as to be connectedbetween the second terminal of the first transistor 31 and the gateelectrode of the third transistor 33 through the first terminal and thesecond terminal thereof. Note that when the shift register including aplurality of pulse output circuits in this embodiment is included in asignal line driver circuit having a larger number of stages than a scanline driver circuit, the ninth transistor 39 may be omitted, which isadvantageous in that the number of transistors is reduced.

Note that an oxide semiconductor is used for active layers of the firstto thirteenth transistors 31 to 43; thus, the off-state current of thetransistors can be reduced, the on-state current and field effectmobility can be increased, and the degree of deterioration of thetransistors can be reduced; thus a malfunction in a circuit can bereduced. Further, the degree of deterioration of the transistor formedusing oxide semiconductor caused by applying high potential to the gateelectrode is small as compared to the transistor formed using amorphoussilicon. Therefore, even when the first power supply potential VDD issupplied to a power supply line to which the second power supplypotential VCC is supplied, similar operation can be performed, and thenumber of power supply lines which are provided in a circuit can bereduced, so that the circuit can be miniaturized.

Note that a similar effect is obtained even when the connection relationis changed so that a clock signal that is supplied to the gate electrodeof the seventh transistor 37 from the third input terminal 23 and aclock signal that is supplied to the gate electrode of the eighthtransistor 38 from the second input terminal 22 may be supplied from thesecond input terminal 22 and the third input terminal 23, respectively.In this case, in the shift register illustrated in FIG. 22A, the stateis changed from the state where both the seventh transistor 37 and theeighth transistor 38 are turned on, to the state where the seventhtransistor 37 is turned off and the eighth transistor 38 is turned on,and then to the state where both the seventh transistor 37 and theeighth transistor 38 are turned off; thus, the fall in a potential ofthe node B due to a fall in the potentials of the second input terminal22 and the third input terminal 23 is caused twice by a fall in thepotential of the gate electrode of the seventh transistor 37 and a fallin the potential of the gate electrode of the eighth transistor 38. Onthe other hand, in the case where a state of the seventh transistor 37and the eighth transistor 38 in the shift register illustrated in FIG.22A is changed in such a manner that both the seventh transistor 37 andthe eighth transistor 38 are turned on, then the seventh transistor 37is turned on and the eighth transistor 38 is turned off, and then theseventh transistor 37 and the eighth transistor 38 are turned off, thefall in potential of the node B, which is caused by a fall in potentialsof the second input terminal 22 and the third input terminal 23, iscaused only once by a fall in the potential of the gate electrode of theeighth transistor 38. Accordingly, the connection relation, that is, theclock signal CK3 is supplied to the gate electrodes (the lower electrodeand the upper electrode) of the seventh transistor 37 through the thirdinput terminal 23 and the clock signal CK2 is supplied to the gateelectrodes (the lower gate electrode and the upper gate electrode) ofthe eighth transistor 38 through the second input terminal 22, ispreferable. That is because the number of times of the change in thepotential of the node B can be reduced, whereby the noise can bereduced.

In this way, in a period during which the potentials of the first outputterminal 26 and the second output terminal 27 are held at the L level,the H level signal is regularly supplied to the node B; therefore,malfunction of a pulse output circuit can be suppressed.

This embodiment can be implemented in combination with embodiments abovementioned.

Embodiment 10

In a liquid crystal display device according to one embodiment of thepresent invention, a highly reliable thin film transistor with highmobility and on-state current is used; therefore, the liquid crystaldisplay device according to one embodiment of the present invention hashigh contrast and high visibility. In this embodiment, a structure ofthe liquid crystal display device according to one embodiment of thepresent invention will be described.

FIG. 23 is a cross-sectional view of a pixel of a liquid crystal displaydevice according to one embodiment of the present invention, as anexample. A thin film transistor 1401 illustrated in FIG. 23 has a gateelectrode 1402 formed over an insulating surface, a gate insulating film1403 over the gate electrode, an oxide semiconductor film 1404 which isover the gate insulating film 1403 and which overlaps with the gateelectrode 1402, and a pair of a conductive film 1406 a and a conductivefilm 1406 b which function as a source electrode and a drain electrodeand which are sequentially stacked over the oxide semiconductor film1404. Further, the thin film transistor 1401 may include an insulatingfilm 1407 formed over the oxide semiconductor film 1404 as itscomponent. The insulating film 1407 is formed so as to cover the gateelectrode 1402, the gate insulating film 1403, the oxide semiconductorfilm 1404, the conductive film 1406 a, and the conductive film 1406 b.

Note that in this embodiment, the source electrode and the drainelectrode which are formed in accordance with the manufacturing methoddescribed in Embodiment 1 are given as an example; however, the sourceelectrode and the drain electrode which are formed in accordance withthe manufacturing method described in any of Embodiments 2 to 4 may beused.

An insulating film 1408 is formed over the insulating film 1407. Part ofthe insulating film 1407 and the insulating film 1408 is provided withan opening, and a pixel electrode 1410 is formed so as to be in contactwith one of the conductive films 1406 b in the opening.

Further, a spacer 1417 for controlling a cell gap of a liquid crystalelement is formed over the insulating film 1408. An insulating film isetched to have a desired shape, so that the spacer 1417 can be formed. Acell gap may also be controlled by dispersing a filler over theinsulating film 1408.

An alignment film 1411 is formed over the pixel electrode 1410. Further,a counter electrode 1413 is provided in a position opposed to the pixelelectrode 1410, and an alignment film 1414 is formed on the side of thecounter electrode 1413 which is close to the pixel electrode 1410. Thealignment film 1411 and the alignment film 1414 can be formed using anorganic resin such as polyimide or polyvinyl alcohol. Alignmenttreatment such as rubbing is performed on their surfaces in order toalign liquid crystal molecules in certain direction. Rubbing can beperformed by rolling a roller wrapped with cloth of nylon or the likewhile applying pressure on the alignment films so that the surfaces ofthe alignment films are rubbed in certain direction. Note that it isalso possible to form the alignment films 1411 and 1414 that havealignment characteristics by using an inorganic material such as siliconoxide with an evaporation method, without alignment process.

Furthermore, a liquid crystal 1415 is provided in a region which issurrounded by a sealant 1416 between the pixel electrode 1410 and thecounter electrode 1413. Injection of the liquid crystal 1415 may beperformed with a dispenser method (dripping method) or a dipping method(pumping method). Note that a filler may be mixed in the sealant 1416.

The liquid crystal element formed using the pixel electrode 1410, thecounter electrode 1413, and the liquid crystal 1415 may overlap with acolor filter through which light in a particular wavelength region canpass. The color filter may be formed on a substrate (counter substrate)1420 provided with the counter electrode 1413. The color filter can beselectively formed by photolithography after application of an organicresin such as an acrylic-based resin in which pigment is dispersed onthe substrate 1420. Alternatively, the color filter can be selectivelyformed by etching after application of a polyimide-based resin in whichpigment is dispersed on the substrate 1420. Alternatively, the colorfilter can be selectively formed with a droplet discharge method such asan ink jet method.

A light-blocking film which can block light may be formed in the pixelsso that disclination due to variations between the pixels in thealignment of the liquid crystal 1415 is prevented from seeing. Thelight-blocking film can be formed using an organic resin containing ablack pigment such as a carbon black or titanium lower oxide.Alternatively, a film of chromium can be used for the light-blockingfilm.

The pixel electrode 1410 and the counter electrode 1413 can be formedusing a transparent conductive material such as indium tin oxideincluding silicon oxide (ITSO), indium tin oxide (ITO), zinc oxide(ZnO), indium zinc oxide (IZO), or gallium-doped zinc oxide (GZO), forexample. Note that this embodiment describes an example of manufacturinga transmissive type liquid crystal element by using a light-transmittingconductive film for the pixel electrode 1410 and the counter electrode1413; however, one embodiment of the present invention is not limited tothis structure. The liquid crystal display device according to oneembodiment of the present invention may be a transreflective liquidcrystal display device or a reflective liquid crystal display device.

Although a liquid crystal display device of a TN (twisted nematic) modeis described in this embodiment, the thin film transistor of the presentinvention can be used for other liquid crystal display devices of a VA(vertical alignment) mode, an OCB (optically compensated birefringence)mode, an IPS (in-plane-switching) mode, and the like.

Alternatively, liquid crystal exhibiting a blue phase for which analignment film is unnecessary may be used. A blue phase is one of liquidcrystal phases, which is generated just before a cholesteric phasechanges into an isotropic phase while temperature of cholesteric liquidcrystal is increased. Since the blue phase is generated within an onlynarrow range of temperature, liquid crystal composition containing achiral agent at 5 wt % or more so as to improve the temperature range isused for the liquid crystal 1415. The liquid crystal compositionincluding liquid crystal exhibiting a blue phase and a chiral agent hasa short response time of greater than or equal to 10 μsec and less thanor equal to 100 μsec and is optically isotropic; therefore, alignmenttreatment is not necessary and viewing angle dependence is small.

FIG. 24 illustrates an example of a perspective view showing a structureof a liquid crystal display device of the present invention. The liquidcrystal display device illustrated in FIG. 24 is provided with a liquidcrystal panel 1601 in which a liquid crystal element is formed between apair of substrates; a first diffusion plate 1602; a prism sheet 1603; asecond diffusion plate 1604; a light guide plate 1605; a reflectionplate 1606; a light source 1607; and a circuit substrate 1608.

The liquid crystal panel 1601, the first diffusion plate 1602, the prismsheet 1603, the second diffusion plate 1604, the light guide plate 1605,and the reflection plate 1606 are sequentially stacked. The light source1607 is provided at an end portion of the light guide plate 1605. Theliquid crystal panel 1601 is uniformly irradiated with light from thelight source 1607 which is diffused inside the light guide plate 1605,due to the first diffusion plate 1602, the prism sheet 1603, and thesecond diffusion plate 1604.

Although the first diffusion plate 1602 and the second diffusion plate1604 are used in this embodiment, the number of diffusion plates is notlimited thereto. The number of diffusion plates may be one, or may bethree or more. It is acceptable as long as the diffusion plate isprovided between the light guide plate 1605 and the liquid crystal panel1601. Therefore, a diffusion plate may be provided only on the sidecloser to the liquid crystal panel 1601 than the prism sheet 1603, ormay be provided only on the side closer to the light guide plate 1605than the prism sheet 1603.

Further, the cross section of the prism sheet 1603 is not limited to asawtooth-shape illustrated in FIG. 24. The prism sheet 1603 may have ashape with which light from the light guide plate 1605 can beconcentrated on the liquid crystal panel 1601 side.

The circuit substrate 1608 is provided with a circuit which generatesvarious kinds of signals input to the liquid crystal panel 1601, acircuit which processes the signals, or the like. In FIG. 24, thecircuit substrate 1608 and the liquid crystal panel 1601 are connectedto each other via a flexible printed circuit (FPC) 1609. Note that thecircuit may be connected to the liquid crystal panel 1601 by using achip on glass (COG) method, or part of the circuit may be connected tothe FPC 1609 by using a chip on film (COF) method.

FIG. 24 illustrates an example in which the circuit substrate 1608 isprovided with a control circuit which controls driving of the lightsource 1607 and the control circuit and the light source 1607 areconnected to each other via the FPC 1610. Note that the above-describedcontrol circuit may be formed over the liquid crystal panel 1601. Inthat case, the liquid crystal panel 1601 and the light source 1607 areconnected to each other via an FPC or the like.

Although FIG. 24 illustrates as an example of an edge-light type lightsource in which the light source 1607 is disposed at an end portion ofthe liquid crystal panel 1601, a liquid crystal display device of thepresent invention may be a direct-below type which includes the lightsource 1607 disposed directly below the liquid crystal panel 1601.

This embodiment can be implemented by being combined as appropriate withany of the above-described embodiments.

Embodiment 11

In this embodiment, a structure of a light-emitting device including thethin film transistor according to one embodiment of the presentinvention for a pixel will be described. In this embodiment, across-sectional structure of a pixel in the case where a transistor fordriving a light-emitting element is an n-channel transistor is describedwith reference to FIGS. 25A to 25C. Although the case where a firstelectrode is a cathode and a second electrode is an anode is describedin FIGS. 25A to 25C, the first electrode may be an anode and the secondelectrode may be a cathode as well.

FIG. 25A is the cross-sectional view of a pixel in the case where ann-channel transistor is employed as a transistor 6031, and light emittedfrom a light-emitting element 6033 is extracted from a first electrode6034. The transistor 6031 is covered with an insulating film 6037, andover the insulating film 6037, a bank 6038 having an opening is formed.In the opening of the bank 6038, the first electrode 6034 is partlyexposed, and the first electrode 6034, an electroluminescent layer 6035,and a second electrode 6036 are sequentially stacked in the opening.

The first electrode 6034 is formed using a material or to a thicknesssuch that light transmits therethrough, and can be formed using amaterial having a low work function of a metal, an alloy, anelectrically conductive compound, a mixture thereof, or the like.Specifically, an alkaline metal such as Li or Cs, an alkaline earthmetal such as Mg, Ca, or Sr, an alloy containing such metals (e.g.,Mg:Ag, Al:Li, or Mg:In), a compound of such materials (e.g., calciumfluoride or calcium nitride), or a rare-earth metal such as Yb or Er canbe used. Further, in the case where an electron injection layer isprovided, another conductive layer such as an aluminum layer may be usedas well. Then, the first electrode 6034 is formed to a thickness suchthat light transmits therethrough (preferably, approximately 5 nm to 30nm). Furthermore, the sheet resistance of the first electrode 6034 maybe suppressed by formation of a light-transmitting conductive layer of alight-transmitting oxide conductive material so as to be in contact withand over or under the above-described conductive layer with a thicknesssuch that light transmits therethrough. Alternatively, the firstelectrode 6034 may be formed using only a conductive layer of anotherlight-transmitting oxide conductive material such as indium tin oxide(ITO), zinc oxide (ZnO), indium zinc oxide (IZO), or gallium-doped zincoxide (GZO). Furthermore, a mixture in which zinc oxide (ZnO) is mixedat 2% to 20% in indium tin oxide including ITO and silicon oxide(hereinafter referred to as ITSO) or in indium oxide including siliconoxide may be used as well. In the case of using the light-transmittingoxide conductive material, it is preferable to provide an electroninjection layer in the electroluminescent layer 6035.

The second electrode 6036 is formed using a material and to a thicknesssuch that light is reflected or blocked, and can be formed using amaterial suitable for being used as an anode. For example, asingle-layer film including one or more of titanium nitride, zirconiumnitride, titanium, tungsten, nickel, platinum, chromium, silver,aluminum, and the like, a stacked layer of a titanium nitride film and afilm including aluminum as a main component, a three-layer structure ofa titanium nitride film, a film including aluminum as a main component,and a titanium nitride film, or the like can be used for the secondelectrode 6036.

The electroluminescent layer 6035 is formed using a single layer or aplurality of layers. When the electroluminescent layer 6035 is formedwith a plurality of layers, these layers can be classified into a holeinjection layer, a hole transport layer, a light-emitting layer, anelectron transport layer, an electron injection layer, and the like inview of the carrier transporting property. In the case where theelectroluminescent layer 6035 includes at least one of a hole injectionlayer, a hole transport layer, an electron transport layer, and anelectron injection layer in addition to a light-emitting layer, theelectron injection layer, the electron transport layer, thelight-emitting layer, the hole transport layer, and the hole injectionlayer are sequentially stacked over the first electrode 6034. Note thatthe boundary between each layer is not necessarily clear, and there maybe the case where the boundary is unclear since a material for formingeach layer is mixed with each other. Each layer may be formed with anorganic material or an inorganic material. As the organic material, anyof a high molecular weight material, a medium molecular weight material,and a low molecular weight material may be used. Note that the mediummolecular weight material corresponds to a low polymer in which thenumber of repetitions of a structural unit (the degree ofpolymerization) is approximately 2 to 20. A distinction between a holeinjection layer and a hole transport layer is not always distinct, whichis the same as in the sense that a hole transport property (holemobility) is an especially important characteristic. A layer being incontact with the anode is referred to as a hole injection layer and alayer being in contact with the hole injection layer is referred to as ahole transport layer for convenience. The same is also true for theelectron transport layer and the electron injection layer; a layer beingin contact with the cathode is referred to as an electron injectionlayer and a layer being in contact with the electron injection layer isreferred to as an electron transport layer. In some cases, thelight-emitting layer also functions as the electron transport layer, andit is therefore referred to as a light-emitting electron transportlayer, too.

In the case of the pixel illustrated in FIG. 25A, light emitted from thelight-emitting element 6033 can be extracted from the first electrode6034 as shown by a hollow arrow.

Next, a cross-sectional diagram of a pixel in the case where atransistor 6041 is an n-channel transistor, and light emitted from alight-emitting element 6043 is extracted from a second electrode 6046side is illustrated in FIG. 25B. The transistor 6041 is covered with aninsulating film 6047, and over the insulating film 6047, a bank 6048having an opening is formed. In the opening of the bank 6048, a firstelectrode 6044 is partly exposed, and the first electrode 6044, anelectroluminescent layer 6045, and the second electrode 6046 aresequentially stacked in the opening.

The first electrode 6044 is formed using a material and to a thicknesssuch that light is reflected or blocked, and can be formed using amaterial having a low work function of a metal, an alloy, anelectrically conductive compound, a mixture thereof, or the like.Specifically, an alkaline metal such as Li or Cs, an alkaline earthmetal such as Mg, Ca, or Sr, an alloy containing such metals (e.g.,Mg:Ag, Al:Li, or Mg:In), a compound of such materials (e.g., calciumfluoride or calcium nitride), or a rare-earth metal such as Yb or Er canbe used. Further, in the case where an electron injection layer isprovided, another conductive layer such as an aluminum layer may be usedas well.

The second electrode 6046 is formed using a material or to a thicknesssuch that light transmits therethrough, and formed using a materialsuitable for being used as an anode. For example, anotherlight-transmitting oxide conductive material such as indium tin oxide(ITO), zinc oxide (ZnO), indium zinc oxide (IZO), or gallium-doped zincoxide (GZO) can be used for the second electrode 6046. Further, amixture in which zinc oxide (ZnO) is mixed at 2% to 20% in indium tinoxide including ITO and silicon oxide (hereinafter referred to as ITSO)or in indium oxide including silicon oxide may be used as well for thesecond electrode 6046. Furthermore, other than the above-describedlight-transmitting oxide conductive material, a single-layer filmincluding one or more of titanium nitride, zirconium nitride, titanium,tungsten, nickel, platinum, chromium, silver, aluminum, and the like, astacked layer of a titanium nitride film and a film including aluminumas a main component, a three-layer structure of a titanium nitride film,a film including aluminum as a main component, and a titanium nitridefilm, or the like can be used for the second electrode 6046. However, inthe case of using a material other than the light-transmitting oxideconductive material, the second electrode 6046 is formed to a thicknesssuch that light transmits therethrough (preferably, approximately 5 nmto 30 nm).

The electroluminescent layer 6045 can be formed in a manner similar tothat of the electroluminescent layer 6035 of FIG. 25A.

In the case of the pixel illustrated in FIG. 25B, light emitted from thelight-emitting element 6043 can be extracted from the second electrode6046 side as shown by a hollow arrow.

Next, a cross-sectional view of a pixel in the case where a transistor6051 is an n-channel transistor, and light emitted from a light-emittingelement 6053 is extracted from a first electrode 6054 side and a secondelectrode 6056 side is illustrated in FIG. 25C. The transistor 6051 iscovered with an insulating film 6057, and over the insulating film 6057,a bank 6058 having an opening is formed. In the opening of the bank6058, the first electrode 6054 is partly exposed, and the firstelectrode 6054, an electroluminescent layer 6055, and the secondelectrode 6056 are sequentially stacked in the opening.

The first electrode 6054 can be formed in a manner similar to that ofthe first electrode 6034 in FIG. 25A. The second electrode 6056 can beformed in a manner similar to that of the second electrode 6046 of FIG.25B. The electroluminescent layer 6055 can be formed in a manner similarto that of the electroluminescent layer 6035 of FIG. 25A.

In the case of the pixel illustrated in FIG. 25C, light emitted from thelight-emitting element 6053 can be extracted from both sides of thefirst electrode 6054 and the second electrode 6056 as shown by hollowarrows.

This embodiment can be implemented in combination with any of the otherembodiments as appropriate.

Example 1

A semiconductor device according to one embodiment of the presentinvention is used, so that a highly reliable electronic device whichoperates at high speed can be provided. In addition, a semiconductordisplay device according to one embodiment of the present invention isused, so that a highly reliable electronic device capable of displayingan image with high contrast and high visibility can be provided.

Moreover, in the semiconductor device of the present invention, the heattreatment temperature in a manufacturing process can be suppressed;therefore, a highly reliable thin film transistor with excellentcharacteristics can be formed even when the thin film transistor isformed over a substrate formed using a flexible synthetic resin of whichheat resistance is lower than that of glass, such as plastic.Accordingly, with the use of the manufacturing method according to oneembodiment of the present invention, a highly reliable, lightweight, andflexible semiconductor device can be provided. Examples of a plasticsubstrate include polyester typified by polyethylene terephthalate(PET), polyethersulfone (PES), polyethylene naphthalate (PEN),polycarbonate (PC), polyetheretherketone (PEEK), polysulfone (PSF),polyetherimide (PEI), polyarylate (PAR), polybutylene terephthalate(PBT), polyimide, an acrylonitrile-butadiene-styrene resin, polyvinylchloride, polypropylene, polyvinyl acetate, an acrylic resin, and thelike.

The semiconductor device according to one embodiment of the presentinvention can be used for display devices, laptops, or image reproducingdevices provided with recording media (typically, devices whichreproduce the content of recording media such as digital versatile discs(DVDs) and have displays for displaying the reproduced images). Otherthan the above, as an electronic device which can use the semiconductordevice according to one embodiment of the present invention, mobilephones, portable game machines, portable information terminals, e-bookreaders, video cameras, digital still cameras, goggle-type displays(head mounted displays), navigation systems, audio reproducing devices(e.g., car audio systems and digital audio players), copiers,facsimiles, printers, multifunction printers, automated teller machines(ATM), vending machines, and the like can be given. FIGS. 26A to 26Eillustrate specific examples of these electronic devices.

FIG. 26A illustrates an e-book reader including a housing 7001, adisplay portion 7002, and the like. The semiconductor display deviceaccording to one embodiment of the present invention can be used for thedisplay portion 7002. The semiconductor display device according to oneembodiment of the present invention is used for the display portion7002, so that a highly reliable e-book reader capable of displaying animage with high contrast and high visibility can be provided. Thesemiconductor device according to one embodiment of the presentinvention can be used for an integrated circuit used for controllingdriving of the e-book reader, so that a highly reliable e-book readerwhich can operate at high speed can be provided. When a flexiblesubstrate is used, a semiconductor device and a semiconductor displaydevice can have flexibility, whereby a user-friendly e-book reader whichis flexible and lightweight can be provided.

FIG. 26B illustrates a display device including a housing 7011, adisplay portion 7012, a supporting base 7013, and the like. Thesemiconductor display device according to one embodiment of the presentinvention can be used for the display portion 7012. The semiconductordisplay device according to one embodiment of the present invention isused for the display portion 7012, so that a highly reliable displaydevice capable of displaying an image with high contrast and highvisibility can be provided. The semiconductor device according to oneembodiment of the present invention can be used for an integratedcircuit used for controlling driving of the display device, so that ahighly reliable display device which can operate at high speed can beprovided. Note that a display device includes all display devices fordisplaying information, such as display devices for personal computers,for receiving television broadcast, and for displaying advertisement, inits category.

FIG. 26C illustrates a display device including a housing 7021, adisplay portion 7022, and the like. The semiconductor display deviceaccording to one embodiment of the present invention can be used for thedisplay portion 7022. The semiconductor display device according to oneembodiment of the present invention is used for the display portion7022, so that a highly reliable display device capable of displaying animage with high contrast and high visibility can be provided. Thesemiconductor device according to one embodiment of the presentinvention can be used for an integrated circuit used for controllingdriving of the display device, so that a highly reliable display devicewhich can operate at high speed can be provided. When a flexiblesubstrate is used, a semiconductor device and a semiconductor displaydevice can have flexibility, whereby a user-friendly display devicewhich is flexible and lightweight can be provided. Accordingly, asillustrated in FIG. 26C, a display device can be used while being fixedto fabric or the like, and an application range of the display device isdramatically widened.

FIG. 26D illustrates a portable game machine including a housing 7031, ahousing 7032, a display portion 7033, a display portion 7034, amicrophone 7035, speakers 7036, an operation key 7037, a stylus 7038,and the like. The semiconductor display device according to oneembodiment of the present invention is used for the display portion 7033and the display portion 7034, so that a highly reliable portable gamemachine capable of displaying an image with high contrast and highvisibility can be provided. The semiconductor device according to oneembodiment of the present invention can be used for an integratedcircuit used for controlling driving of the portable game machine, sothat a highly reliable portable game machine which can operate at highspeed can be provided. Although the portable game machine illustrated inFIG. 26D includes two display portions 7033 and 7034, the number ofdisplay portions included in the portable game machine is not limited totwo.

FIG. 26E illustrates a mobile phone which includes a housing 7041, adisplay portion 7042, an audio input portion 7043, an audio outputportion 7044, operation keys 7045, a light-receiving portion 7046, andthe like. Light received in the light-receiving portion 7046 isconverted into electrical signals, whereby an outside image can bedownloaded. The semiconductor display device according to one embodimentof the present invention can be used for the display portion 7042. Thesemiconductor display device according to one embodiment of the presentinvention is used for the display portion 7042, so that a highlyreliable mobile phone capable of displaying an image with high contrastand high visibility can be provided. The semiconductor device accordingto one embodiment of the present invention can be used for an integratedcircuit used for controlling driving of the mobile phone, so that ahighly reliable mobile phone which can operate at high speed can beprovided.

This example can be implemented by being combined as appropriate withany of the above-described embodiments.

This application is based on Japanese Patent Application serial no.2009-242256 filed with Japan Patent Office on Oct. 21, 2009, the entirecontents of which are hereby incorporated by reference.

1. A semiconductor device comprising: a gate electrode; a gateinsulating film over the gate electrode; an oxide semiconductor filmover the gate insulating film, the oxide semiconductor film comprisingindium, gallium, and zinc; a source electrode over the oxidesemiconductor film; a drain electrode over the oxide semiconductor film;and an insulating film over the source electrode and the drainelectrode, wherein the gate insulating film is a stack of a siliconnitride film and an aluminum oxide film, and wherein each of the sourceelectrode and the drain electrode is a stack of a tungsten film and analuminum film over the tungsten film.
 2. The semiconductor deviceaccording to claim 1, wherein an off-state current of a transistorcomprising the oxide semiconductor film is less than or equal to 10⁻¹³ Aand a subthreshold swing of the transistor is less than or equal to 0.1V/dec.
 3. The semiconductor device according to claim 1, wherein one ofthe source electrode and the drain electrode is in contact with a sidesurface of the oxide semiconductor film.
 4. The semiconductor deviceaccording to claim 1, wherein a carrier concentration of the oxidesemiconductor film is less than 1×10¹⁸/cm³.
 5. The semiconductor deviceaccording to claim 1, wherein the oxide semiconductor film comprisesindium, gallium, and zinc.
 6. A semiconductor device comprising: a gateelectrode; a gate insulating film over the gate electrode; an oxidesemiconductor film over the gate insulating film; a source electrodeover the oxide semiconductor film; a drain electrode over the oxidesemiconductor film; and an insulating film over the source electrode andthe drain electrode, wherein each of the source electrode and the drainelectrode comprises a first conductive film and a second conductive filmover the first conductive film, wherein the first conductive filmcomprises tungsten or molybdenum, and wherein the second conductive filmcomprises a metal with a lower electronegativity than anelectronegativity of hydrogen.
 7. The semiconductor device according toclaim 6, wherein an off-state current of a transistor comprising theoxide semiconductor film is less than or equal to 10⁻¹³ A and asubthreshold swing of the transistor is less than or equal to 0.1 V/dec.8. The semiconductor device according to claim 6, wherein one of thesource electrode and the drain electrode is in contact with a sidesurface of the oxide semiconductor film.
 9. The semiconductor deviceaccording to claim 6, wherein a carrier concentration of the oxidesemiconductor film is less than 1×10¹⁸/cm³.
 10. The semiconductor deviceaccording to claim 6, wherein the oxide semiconductor film comprisesindium, gallium, and zinc.